A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

A method and system for processing information. An apparatus divides target information into N pieces of divided data using a secret sharing scheme in which a predetermined number (K) of pieces of the N pieces of divided data is required to restore the target information, wherein N>K. The apparatus is an information processing device or an external storage device. The apparatus selects M pieces from the N pieces (K<M<N). After selecting the M pieces, the M pieces are stored in the external storage device which limits a totality of pieces of the N pieces being stored on the external storage device to the M pieces. After storing the M pieces, the target information is restored from at least K pieces of the N pieces after which D pieces of the M pieces in the external storage device are destroyed (D>M−K).

A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

A controller is coupled to a non-volatile memory device and a host. The controller is configured to perform a cyclic redundancy check on map data associated with user data stored in the memory device, generate an encryption code based on a logical address included in the map data, generate encrypted data through a logical operation on the encryption code and the map data, and transmit the encrypted data to the host.

The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

A device that provides for redundancy of error correction encoded data includes at least one processor circuit. The at least one processor circuit is configured to perform error correction encoding on data items to generate corresponding codewords, where at least one of the data items may have a different length than at least one other of the data items and each of the codewords is the same length. The at least one processor circuit is further configured to generate a redundancy data item based at least in part on the codewords. The at least one processor circuit is further configured to write the codewords and the redundancy data item to separate blocks of at least one flash memory circuit.

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.