A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

The present disclosure includes apparatuses, methods, and systems for error identification on executed code. An embodiment includes memory and circuitry configured to read data stored in a secure array of the memory, identify a different memory having an error correcting code (ECC) corresponding to the read data of the memory, execute an integrity check to compare the ECC to the read data of the memory; and take an action in response to the comparison of the read data of the memory and the ECC, wherein the comparison indicates that the ECC identified an error in the read data of the memory.

A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.

An error detection and correction method for a flash memory includes: a setting step, setting selection information to select a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multiple-bit error detection and correction; and an executing step, performing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

A system, method, and product for flexible RAID layouts in a storage system, including: determining a reliability of an individual storage device of a plurality of storage devices, the individual storage device containing a plurality of portions of a Redundant Array of Independent Disks (RAID) stripe in a storage system, wherein the RAID stripe includes user data and inter-device parity data; detecting a change in the reliability of the individual storage device that contains the portion corresponding to the RAID stripe; and changing an amount of intra-device protection corresponding to the RAID stripe by decreasing, in the RAID stripe, an amount of space used to store the inter-device protection data.

A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.

A system, method, and product for flexible RAID layouts in a storage system, including: determining a reliability of an individual storage device of a plurality of storage devices, the individual storage device containing a plurality of portions of a Redundant Array of Independent Disks (RAID) stripe in a storage system, wherein the RAID stripe includes user data and inter-device parity data; detecting a change in the reliability of the individual storage device that contains the portion corresponding to the RAID stripe; and changing an amount of intra-device protection corresponding to the RAID stripe by decreasing, in the RAID stripe, an amount of space used to store the inter-device protection data.

A method includes obtaining input encoded data slices from memory of the storage network, where the input encoded data slices include a set of encoded data slices interspersed with a set of auxiliary data slices, where a data segment was error encoded into the set of encoded data slices, and where auxiliary data was error encoded into the set of auxiliary data slices. The method further includes obtaining de-selection information associated with the input encoded data slices and de-selecting the sequence of input encoded data slices based on the de-selection information to produce deselected encoded data slices. The method further includes error decoding at least a decode threshold number of encoded data slices of the deselected encoded data slices in accordance with error decoding parameters to reproduce the data segment. The method further includes outputting the data segment to a requesting computing device of the storage network.