The invention relates to a system (1), comprising at least two asynchronous computers (2-i), on each of which at least one application (A) is executed, which provides control data (SD) for at least one actuation system (3), wherein the provided control data (SD) are transmitted by a control-authorized computer (2-i) that assumes a master computer status (M-RS) to the actuation system (3) for the control thereof, wherein the computers (2-i) of the system (1) cyclically exchange state data (ZD) and performance data (LD) with each other by means of a data interface in a data exchange (DAS), wherein the computers (2-i) each determine, on the basis of the state and performance data (ZD.sub.opp, LD.sub.opp) received from other computers (2-j) and on the basis of the computer's own state and performance data (ZD.sub.own, LD.sub.own, in a master/slave selection (MSA) performed on the computer (2-i), a computer status (RS) as a control-authorized or non-control-authorized computer (2-i) to be assumed by the particular computer (2-i) itself.

A subsea production system for producing fluids from a subsea well in a subsea field. The production system includes a production facility and a production umbilical connecting the subsea well with the production facility. The production system also includes a control system for controlling production from the subsea well. The control system includes a first redundant master control station system (redundant MCS) at a first location, the redundant MCS capable of controlling production from the subsea well. The control system also includes a second redundant MCS at a second location, the second redundant MCS capable of controlling production from the subsea well. The redundant MCSs are synchronized to keep the same electronic data at both locations and to prevent conflicts in control signals from the redundant MCSs.

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.

A safety communication scheme for a safety-critical system which includes two or more higher level units that have voting capabilities and one or two sets of lower level units that do not have voting capabilities, involves using one channel between the high and low level units for safety and two channels for redundancy.

In part, disclosure relates to a method of regulating checkpointing in an active active fault tolerant system. The method includes receiving a request from a client through a network at a primary computer; copying, by the primary computer, the request from the client to a secondary computer; processing the request from the client, using the primary computer, to generate a primary computer result; processing the copy of the request from the client, using the secondary computer, to generate a secondary computer result; comparing the primary computer result and the secondary computer result to obtain a comparison metric; determining whether a minimum checkpoint interval has been met or exceeded; and if the minimum checkpoint interval has not been met or exceeded, delay initiating a checkpoint process from primary computer to secondary computer.

A method and a system are provided for data management in a transport device, in particular in a train. In a first comparison, a first count value stored in a first control device is compared with a count value stored in a second control device. In a second comparison, a count value selected from the first and second count values on the basis of a result of the first comparison is compared with a control count value stored in a safety device. On the basis of a result of the second comparison, control data stored in the safety device and associated with the control count value are acquired by the first or second control device.

Internet-of-Things (“IoT”) controllers built using hardened industrial technologies which improve functionality and reliability, such as a fixed-loop model in which a loop is repeated with configured time periodicity where sensors are queried, sensor responses are read, configured calculations are performed, and logic rules are evaluated resulting in decisions made and outputs activated. A variety of redundancy techniques are utilized to provide continuous non-stop operation of IoT controllers to compensate for possible hardware and software failures. Robust IoT controller redundancy also allows periodic maintenance, software updates and security patch installation without shutting down the IoT controllers.

An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Examples may include intercepting packets outputted from a primary virtual machine (PVM) hosted by a first server and converting one or more fields of protocol headers for each intercepted packet such that output-packet-similarity may be increased between the PVM outputted packets and packets outputted by a secondary virtual machine (SVM) hosted by a second server.

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.