A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.

An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.

Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

A method includes identifying multiple apportionments, where each apportionment identifies numbers of bit copies to be stored in at least one memory for at least some bits of a data value. The method also includes, for each apportionment, estimating a numerical error associated with use of the apportionment with a specified function, where the numerical error is estimated by creating errors in bit copies of multiple data values processed using the specified function. The method further includes combining portions of different ones of the apportionments having lower estimated numerical errors to create multiple derived apportionments. The method also includes, for each derived apportionment, estimating a numerical error associated with use of the derived apportionment with the specified function. In addition, the method includes selecting a final apportionment for use with the specified function, where the final apportionment includes or is based on at least one of the derived apportionments.

An indication is received. The indication is of an address in a first page in virtual memory used by an application with a static memory corruption. A loadable kernel module will monitor the address. Access to the first page in virtual memory is changed from read/write access to read only access. A second page in virtual memory is created with read/write access. Whether a page fault occurs on the first page in virtual memory during the execution of the application with the static memory corruption is determined.

A system includes a plurality of storage units each including a network port operably coupled to the network, where one or more storage vaults is associated with the plurality of storage units and each storage vault of the one or more storage vaults represents a software-constructed grouping of storage units of the plurality of storage units, where the software-constructed grouping of storage units stores encoded data slices, where a data segment is encoded using an information dispersal algorithm to produce the encoded data slices, and where a storage unit: receives, via the network port, a request regarding the data segment stored in the software-constructed grouping of storage units, obtains, from a data structure pertaining to the software-constructed grouping of storage units, information regarding the request, determines whether the request is valid based on the information regarding the request, and when the request is valid, the storage unit executes the request.

A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

Techniques described and suggested herein include systems and methods for optimizing performance characteristics by differentiating data storage device types for data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be stored on different types of data storage devices to optimize for various retrieval use cases and implemented environments. Implementing systems may monitor various performance characteristics so as to adaptively account for changes to some or all of the monitored parameters.