A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.

An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data. A difference between the associated error detection code and the verification error detection code triggers an error in the translation response.

Filter information including a first temperature level and a second temperature level associated with a test process to be executed on one or more memory components is determined. Information associated with the test process is distributed to a first test component including a first set of memory components and a first temperature control component and a second test component including a second set of memory components and a second temperature control component. First feedback information associated with execution of the test process by the first test component at the first temperature level established by the first temperature control component is received. Second feedback information associated with execution of the test process by the second test component at the second temperature level established by the second temperature control component is received. Based on at least one of the first feedback information or the second feedback information, a failure of the test process executed using at least one of the first temperature level or the second temperature level is determined.

A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Certain embodiments may relate to providing increased storage capacity. For instance, a memory storage device may include a motherboard with an external communication interface. The memory storage device may also include a multiple solid-state drives coupled to the motherboard in communication with the external communication interface. Each of the plurality of solid-state drives may include a respective storage controller to manage the distribution of data during a write or read operation to a combination of a primary storage allocation and a redundant storage allocation. The redundant storage allocation may be included in the combination in response to detecting an error condition associated with at least a portion of the primary storage allocation.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Techniques perform storage management. Such techniques involve, in response to an operation to be performed on data in a cache page, determining a first cache page reference corresponding to the cache page, the first cache page reference comprising a pointer value indicating the cache page. Such techniques further involve creating, based on the first cache page reference and the operation, a second cache page reference corresponding to the cache page, the second cache page reference comprising the pointer value. Such techniques further involve performing the operation on the data in the cache page via the second cache page reference. One cache page can correspond to a plurality of cache page references. Additionally, copy of data from one cache page to a further cache page can be effectively avoided, so as to enhance input/output performance and utilization rate of storage space.

An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

Embodiments of the present disclosure are directed to dynamic shadow operations configured to dynamically shadow data-plane resources in a network device. In some embodiments, the dynamic resource shadow operations are used to locally maintain a shadow copy of data plane resources to avoid having to read them through a bus interconnect. In other embodiments, the dynamic shadow framework is used to provide memory protection for hardware resources against SEU failures. The dynamic shadow framework may operate in conjunction with adaptive memory scrubbing operations. In other embodiments, the dynamic shadow infrastructure is used to facilitate fast boot-up and fast upgrade operations.

Method of controlling initialization of nonvolatile memory device, where nonvolatile memory device includes memory cell region including first metal pad and peripheral circuit region including second metal pad and vertically connected to memory cell region by first and second metal pads, includes performing first sensing operation to sense write setting data stored in first memory cells in memory cell region of first memory plane and store first read setting data in first page buffer circuit in peripheral circuit region of first memory plane, performing second sensing operation to sense write setting data stored in second memory cells in memory cell region of second memory plane and store second read setting data in second page buffer circuit in peripheral circuit region of second memory plane and performing dump-down operation to store restored setting data in buffer based on first read setting data and second read setting data.