Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.

An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

A method for recovering a clock signal from a data signal by using a clock recovery module is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module as well as a computer program are described.

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

A synchronizing system including a generation unit for generating a synchronizing pulse from data of an independent clock, the synchronizing pulse being generated in a periodic manner, transmission links to transmit the synchronizing pulse to all the computation units, and in each of the computation units, a control element to compare the synchronizing pulse that has been received to a pulse generated by an internal clock of the computation unit and to detect a compliance or a lack of compliance, a scheduler of each of the computation units activating a sequence of partitions when the synchronizing pulse is received, and this only if the control element has detected a compliance. The synchronizing system is configured to synchronize the computation units in a reliable and accurate manner and to increase the operating safety of these computation units.