An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.

The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.

The invention relates to a method for synchronizing interconnected critical devices comprising servers and clients, each critical device being connected to another critical device by a virtual link, each termination of which is associated with a minimum and a maximum value of transmission time for a data packet, the method, implemented periodically, comprising: the reception of a message at a reception instant, said message comprising at least one time reference determined by a transmitter server, for each message received, the estimation of the current time of the transmitter server on the basis of: the time reference, a value of the internal clock of the current critical device at the current instant and at the reception instant, the minimum value and the maximum value of transmission time of the virtual link between the transmitter server and the current critical device.

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

Systems and methods for timing over a Metro Transport Networking (MTN) path include detecting a specific block in a stream of blocks, wherein each block is encoded based on a line code, and sampling an output of a clock to determine a timestamp reference based on detection of the specific block, and transmitting timing information based on the timestamp reference. The specific block can be a control block. The timing information can be transmitted via a Precision Time Protocol (PTP) message. The timing information can be transmitted via a plurality of subsequent specific blocks.

A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

A geographical hot redundancy method includes: a first master computer transmitting to a second slave computer first input data items and a first execution context for the n.sup.th execution cycle of an application, first and second replicas being respectively executed on the first and second computers; execution of the first replica, updating the first execution context at the n.sup.th cycle end and transmission to the second computer; recovering the first input data items and the first execution context for the n.sup.th cycle as the second input data items and second execution context for the n.sup.th cycle; executing the second replica in the second execution context for the n.sup.th cycle, on the second input data items of the n.sup.th cycle, and updating the second execution context at the end of the n.sup.th cycle; and checking and verifying consistency by comparing first and second execution contexts at the n.sup.th cycle end.

The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.

The invention relates to a method for synchronizing interconnected critical devices comprising servers and clients, each critical device being connected to another critical device by a virtual link, each termination of which is associated with a minimum and a maximum value of transmission time for a data packet, the method, implemented periodically, comprising: the reception of a message at a reception instant, said message comprising at least one time reference determined by a transmitter server, for each message received, the estimation of the current time of the transmitter server on the basis of: the time reference, a value of the internal clock of the current critical device at the current instant and at the reception instant, the minimum value and the maximum value of transmission time of the virtual link between the transmitter server and the current critical device.