A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

A control apparatus includes a first controller configured to generate control signals for controlling an engine or other machine, a second controller configured to generate the control signals for controlling the machine, a transfer circuit, and an arbiter circuit. The transfer circuit is coupled between the machine and the controllers, and is configured to switch from a first state, where the transfer circuit passes the control signals from the first controller to the machine, to a second state, where the transfer circuit passes the control signals from the second controller to the machine, responsive to receiving a first failure signal from the first controller. The arbiter circuit includes three (or more) arbiters, and is configured to control the transfer circuit from the first state to the second state responsive to any two of the three arbiters generating second signals indicative of failure of the first controller.

The method for automated manufacturing of an electronic circuit tolerant to faults by temporal redundancy of maximum order N, comprising a step implemented by computer, according to which every memory cell of the circuit is replaced by a memory block (40) comprising a chain of memory cells in series, and a selection block which, in a temporal redundancy mode of order n1, n1∈[1,N], selects as output data of the memory block the majority content of n1 cells of the block, and can furthermore deliver a fault signal if the contents of the n1 cells differ. Said method is characterized in that the inserted memory blocks allow a dynamic switching from a temporal redundancy mode of order n1 to any other mode of order n2. Said method for N=2, in association with a mechanism for recording with roll-back, allows an error with only a double redundancy instead of a triple redundancy.

Provided herein are an acceleration system and a driving method thereof. The acceleration system includes a configuration memory, and a plurality of processing units which receive works from the configuration memory, perform the received works, and output results of the performed works. Each of the processing units include an n (n is an integer of three or more) number of processing elements which generate an n number of results, and each of which receives one of the works, and a select module which selects, using a majority-vote system, one of the n number of generated results and generates a selected result.

Technology is described for generating a valid token control signal from control signals from a row driver. In one example, a matrix type integrated circuit includes a row driver module and a 2D array of cell elements. The row driver module includes a voting logic module and at least two row drivers configured to generate control signals on at least two communal lines for cell elements of a row of the 2D array. Each row driver is configured to generate control signals on at least three control lines where at least two control lines are the communal lines and coupled to a corresponding communal line of another row driver. The voting logic module is coupled to the at least three control lines of one of the row drivers and configured to generate an output based on the control signals on the at least three control lines.

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Implementations of the present disclosure include setting, by a first consensus node, a timer that runs out before a timeout of a view change; sending, to a second consensus node, a request for one or more consensus messages missing by the first consensus node in response to the timer running out; receiving, from the second consensus node, the one or more consensus messages each digitally signed by a private key of a corresponding consensus node that generates the respective one or more consensus messages; and determining that a block of transactions is valid, if a quantity of commit messages included in the received one or more consensus messages is greater than or equal to 2f+1, where f is a maximum number of faulty nodes that is tolerable by the blockchain based on practical Byzantine fault tolerance.

A fault tolerant consensus generation and communication system and method is described. Each processing node in the system receives a plurality of measurements from a sensor, calculates a consolidated value for the received plurality of measurements, transmits the consolidated value to other processing nodes, receives consolidated values from the other processing nodes, calculates a consensus value based on the calculated consolidated value and the received one or more consolidated values, transmits the calculated consensus value to the other processing nodes, receives consensus values from the other processing nodes, generates a consensus message based on the calculated consensus value, the received one or more consensus values, and a predefined criterion, and, in a case where the consensus message is not present in a consensus queue, adds the consensus message to the consensus queue.

Systems and techniques for digital twin framework for next generation networks are described herein. A digital twin model may be generated for physical nodes of an edge network. The digital twin model may include a digital twin for a physical node of the physical nodes. An error may be identified of the physical node or the digital twin for the physical node. The digital twin model may be updated to halt communication with the physical node or the digital twin of the physical node. A path may be created to another physical node or a digital twin of the another physical node in the digital twin model.

A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.