The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.

Devices systems and methods are disclosed providing a highly fault tolerant Command, Control, and Data Handling (CC&DH) system immune to byzantine faults. The system includes a plurality of High Integrity Computing Elements each capable of delivering data immune to byzantine faults, an arbitrary communication interface, and a number of peripheral devices providing input and output to the system. The system is capable of providing high integrity data immune to byzantine faults throughout the system. Using one greater High Integrity Computing Elements than the number of faults required allows for implementation of a wide range of redundant systems including dual, triple, quad, and beyond redundancy using voting computers. The system is implemented using any number of standard computing elements, which is greater than two, a communication abstraction, data exchange, mission algorithm, and data comparison producing data immune to byzantine errors to the remaining peripherals in the system.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

A data management system including a plurality of servers each having a processor, a memory, and a storage device, the system receiving and storing data using the plurality of servers and multiplexing the data, wherein the servers are provided with: a first determination unit that determines the consistency of the multiplexed data; a second determination unit that has a greater number of allowable server failures than the first determination unit for determining the consistency of the multiplexed data but a greater minimum number of times of server-to-sever communications for determining the consistency of the data; a combination unit that receives a data consistency determination result from the first determination unit or the second determination unit, and that, if the determination result includes consistency guaranteeing data, outputs the consistency guaranteed data; and a data storage unit that stores the data output by the combination unit.

Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

Embodiments enable a database management system (DBMS) to manage two levels of disk failure groups. These two levels of redundancy are achieved by grouping the disks of the disk group for the DBMS into two levels of failure groups (i.e., data sites each containing two or more failure groups of disks). This system of disk grouping allows a DBMS to potentially tolerate the loss of both an entire first site and part of a second site. Such a DBMS uses a multi-level voting system, based on both failure group-level votes and site-level votes, to identify the current version of administrative data structures (ADS) that store key administrative data. In addition to data sites that store database data, the DBMS includes a quorum site with a single quorum failure group that stores a copy of the ADS. The quorum site contributes a site-level vote during a multi-level voting event.

Representative embodiments disclose a consistent, low latency, reliable storage system that uses quorum logic. An odd number of storage nodes are selected to store data for a client application. The odd number allows a quorum to be determined. When data is written to the storage nodes, success is identified if the data is successfully written to a majority of the storage nodes. Similarly, when a read is performed, success is identified if the majority of the storage nodes return the same value written in the same write operation. This is determined by matching a value and a version number for each node. Additional data is written to the storage nodes along with the values to allow the system to identify and repair inconsistencies in the data. In some embodiments, both the current data and prior data are stored to aid in repairing inconsistent data.

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.