A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

A memory controller for dual-channel DDR DIMMs comprises a first memory channel configured to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM, and a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM. The memory controller is configured to determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device, and to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the degraded performance level.

An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.

A remote terminal adapter device is disclosed. The adapter device includes control processors in communication with a bus controller via a dual redundant data bus (e.g., MIL-STD-1553) having primary and secondary data buses or channels. The adapter device includes analog relays connecting the primary and secondary buses to a main remote terminal (RT) device configured for control of an aircraft subsystem. Additional analog relays connect the data bus to one or more auxiliary or additional RTs (e.g., configured to backup the main RT or simulate the controlled subsystem and its responses. The adapter device may monitor the data bus for traffic and allow the redundant RT to access the data bus (from the same remote terminal) address as the main RT by activating and deactivating the analog relays.

The present invention relates to a power and video redundancy system for a display system of a smartboard. More particularly, the present invention relates to a power and video redundancy system applied to a smartboard display system which minimizes the user's inconvenience due to the failure or damage of components and enables the manager to repair or change the parts without the user being aware of the loss or damage.

A programmable display device for a production system that includes a storage device and a plurality of the programmable display devices. The storage device includes a plurality of individual memory areas that store data from the plurality of the programmable display devices individually and are associated with any one of the plurality of the programmable display devices. There is a backup processing unit that loads some or all data that the programmable display device itself retains into an individual memory area associated with the programmable display device itself among the plurality of individual memory areas and a state management unit that updates state management information retained in the storage device when the backup processing unit has performed data update within the individual memory area associated with the programmable display device itself The state management information indicates that data retained by the plurality of individual memory areas have been updated.

A system includes at least one memory including a persistent storage, at least one processor in communication with the at least one memory, a virtual machine associated with a virtual machine memory, and a hypervisor executing on the at least one processor. The hypervisor is configured to map the virtual machine memory to the persistent storage, detect a request to restart a host, and synchronize the virtual machine memory by copying data to the persistent storage for each page of the virtual machine memory that has changed. The hypervisor is also configured to pause the virtual machine prior to the host restarting, save a virtual machine state to the persistent storage, restore the virtual machine state after the host restarts, and resume operation of the virtual machine.

Apparatuses, methods, program products, and systems are presented for interrupt virtualization. An apparatus includes an adapter module that detects a switch from a first physical input/output (“I/O”) adapter associated with a logical partition to a second physical I/O adapter associated with the logical partition. The apparatus includes an interrupt module that updates one or more I/O interrupt management structures for the logical partition so that the logical partition receives I/O interrupt information from the second physical I/O adapter and not the first physical I/O adapter without the logical partition being aware of the switch to the second I/O adapter. The apparatus includes an abstraction module that updates physical device information at a hypervisor for the logical partition to reflect the switch to the second physical I/O device.

Embodiments are directed towards a controller that provides individual network accessibility to a storage drive. The controller may include a first connector operative to couple with a storage-drive connector, a second connector operative to couple with a backplane connector of a multi-storage-drive chassis, memory, and processor. The controller may convert communication received through the first connector into an Ethernet protocol for output through the second connector, and convert communication received through the second connector into a storage-drive protocol for output through the first connector. A physical shape of the controller may fit adjacent to the storage-drive connector and occupy less space than is bounded by peripheral edges of an end of a separate housing of a storage drive coupled to the storage-drive connector. The controller may manage power provided to the storage drive and may coordinate with other controllers to manage power-up sequences of multiple storage drives.