A data processing system (1) comprises a plurality of, e.g. graphics, processing units (11), and a management circuit (12) associated with the processing units and operable to configure the processing units of the plurality of processing units into respective groups of the processing units. The management circuit (12) is configured to always operate with a high level of fault protection, but the groups of the processing units can be selectively operated with either a higher level of fault protection or a lower level of fault protection, by selectively subjecting them to fault detection testing (60).

Provided is a method of operating a system-on-chip (SoC) including a plurality of CPUs. The method includes: receiving a debug request by a first CPU of the CPUs; outputting a first signal to the CPUs by the first CPU in response to the debug request; selecting a second CPU from the CPUs to control the debugging based on the first signal; and performing a debug operation by selecting a debug target block by the second CPU.

An integrated circuit chip comprising: system circuitry comprising interconnect circuitry for transporting transactions; and monitoring circuitry configured to: monitor transactions from the interconnect circuitry comprising transactions between an entity and a specified region of the integrated circuit chip, the entity being associated with a set of one or more access rights for accessing the specified region of the integrated circuit chip; determine from the monitored transactions values of one or more parameters associated with the access to the specified region by the entity to identify whether the entity has breached its access rights; and perform a dedicated action indicative of a breach of the access rights in response to determining from the parameter values that the entity has breached its access rights.

Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

Methods and apparatus relating to characterizing proximity risks within a radio mesh are described. In an embodiment, test manager logic causes periodic testing of one of a first group of processor cores or a second group of processor cores. Each of the first group of processor cores or the second group of processor cores comprises one or more processor cores of a multi-core processor. Memory stores information corresponding to the period testing of the first group of processor cores and the second group of processor cores. A fault signal is to be generated in response to completion of the period testing outside a Fault Tolerant Time Interval (FTTI). Other embodiments are also disclosed and claimed.

A method for testing a multi-core integrated circuit device including a plurality of processing cores includes testing a first processing core on the integrated circuit device utilizing one or more tests. If a first feature on the first processing core fails a first test, the method includes performing a second test on the first processing core that tests the first processing core without the first feature. The method includes determining, based on the second test, if the first processing core is operable without the first feature. If the first processing core is operable without the first feature, the method includes storing information about the first processing core's capabilities in vital product data.

In the present invention, computational efficiency degradation is suppressed when diagnosing a shared storage area in a vehicle control device in which a plurality of computing units are employed. This vehicle control device suppresses computational efficiency degradation by changing an access destination in a storage device while diagnosing a shared storage area that the storage device has.

In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

A method for applying an update includes sending a registration request to an update web service; receiving a delay parameter from the update service; checking for an update; comparing the update release date and the delay parameter with the current date to determine if the update should be installed; and installing the update when the current date is determined to be past the update release date plus the delay parameter.

A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.