A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

Test code and test data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing test code and test data in the non-naturally aligned data boundaries as described herein allows test code and data to be replicated throughout a cache memory while preserving double word and quad word boundaries in segments of the replicated test code and test data. Coherency of the processor memory can be tested when the same cache line from the level two (L2) cache is simultaneously in both the level one (L1) instruction cache and the L1 data cache.

A method, computer program product, and computer system are provided for testing drives in a redundant array of independent disks (RAID) array. The method includes: mirroring data from a selected drive to be tested in a RAID array to spare storage space in the RAID array; and, once the data is successfully mirrored, testing the selected drive to identify a preemptive failure of the selected drive. The RAID may be a traditional RAID (TRAID) array and the spare space may be a spare physical drive independent of array drive members. The RAID array may alternatively be a distributed RAID (DRAID) array and the spare space may be spare capacity spread through the array drive members.

A management controller may be configured to control connectivity among a host system processor, a primary ROM, and a recovery ROM in accordance with a plurality of modes of operation including at least a normal mode that occurs in response to absence of a corruption of the ROM code in which the management controller causes the host system processor to be communicatively coupled to the primary ROM and communicatively decoupled from the recovery ROM, such that the host system processor loads and executes the ROM code during boot of the host system, and a primary ROM recovery mode that occurs in response to presence of the corruption of the ROM code in which the management controller causes the host system processor to be coupled to the primary ROM and the recovery ROM, such that the host system processor loads and executes the recovery code during boot of the host system.

The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet. The Descriptive Tracking Header is further updated based on the result of the comparison of the expected output packet against the corresponding actual output packet and used for the generation of simulation results summary for the purpose of simulation results analysis and failures debug.

A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.

Data is replicated into a memory cache and cache inhibited memory in data segments with segment size that provides non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries allows replicated testing of the memory cache and cache inhibited memory while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases generated for cacheable memory to be replicated and used for cache inhibited memory. The processor can then use a single test replicated in this manner by branching back and using the next slice of the replicated test data in the memory cache and cache inhibited memory.

An approach for erasing data being stored in a data storage apparatus is provided, which may be provided e.g. as an apparatus, as a method, as a system or as a computer program. A sequence of uncompressible data is obtained fulfilling predetermined criteria, which includes a statistical measure indicative of compressibility or uncompressibility of the sequence of uncompressible data meeting a predetermined criterion, wherein the sequence of uncompressible data is divided into one or more blocks of uncompressible data, the sum of the sizes of the one or more blocks of uncompressible data being larger than or equal to the storage capacity of the data storage apparatus. The one or more blocks of uncompressible data is provided to the data storage apparatus for storage therein to overwrite the data currently stored in the data storage apparatus.

An automated test equipment (ATE) system includes a plurality of test blades each coupled to a test blade connector and mounted on a circular track; a central reference clock (CRC) having an origin point at a center of the circle; and a clock/sync connector coupled to the CRC through a zero skew clock connection to one or more sync buses, wherein each instrument utilizes the CRC to coordinate its testing process with another instrument.