The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.

A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.

Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.

A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.

An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.

A virtual device acquires a transaction history between a legacy computing device and a linked device; obtains a first request provided from the legacy computing device based on the transaction history and a first response received from the linked device in response to the first request; receives a second request corresponding to the first request from a new computing device and determines a second response to the second request; and provides test information for the new computing device based on a comparison of the first response and the second response.

A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.

Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.

The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.