Technologies to perform a secure debug of a FPGA are described. In some examples an apparatus comprises an accelerator device comprising processing circuitry to facilitate acceleration of a processing workload executable on a remote processing device, a computer-readable memory to store logic operations executable on the accelerator device, and a debug module. The debug module comprises one or more debug registers to store debug data for the logic operations executable on the accelerator device and processing circuitry to receive, from a debug application on the remote processing device, a memory access request directed to a target debug register of the one or more debug registers, encrypt the debug data in the target debug register to generate encrypted debug data, and return the encrypted debug data to the debug application. Other embodiments are described and claimed.

A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.

A method of confirming an accessory functionality of an accessory device includes obtaining an accessory device description that includes information regarding the accessory device and identifying a test case based on the accessory device description. The test case is configured to evaluate the accessory functionality and includes a test standard. The method also includes performing, by a test device, a test procedure that corresponds to the test case. The test procedure causes the accessory device to perform an action that corresponds to the accessory functionality. The method also includes recording an observation regarding the action, and determining whether a test result corresponds to a pass condition or a fail condition based on a comparison of the observation to the test standard.

A GUI testing device may be configured to execute a testing state machine for interacting with a software application to generate an initial screen of a GUI. The GUI testing device may be configured to determine a current state in the testing state machine based upon a matching trigger target in the initial screen to a given state. The current state may include an operation, and the operation may associate with a trigger target to operate on. The trigger may include a source state, a destination state, and a trigger target. The operation may include a user input operation, and an operation trigger target. The GUI testing device may be configured to perform the operation on the matching trigger target in the initial screen to generate a next screen of the GUI, and advance from the current state to a next state based upon the trigger.

A method for testing an interaction system response to different types of interaction devices is disclosed. A testing computer can execute various sets of interaction device logic during different test interaction. The testing computer can electronically communicate with an access device during test interaction through a conduit mobile device. As a result, the testing computer can electronically communicate with the access device even when the testing computer is remotely located.

A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.

A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

There is provided a system and method for performing system integration on an embedded system of a connected and/or autonomous vehicle. Integration testing may include obtaining one or more requirements and/or specifications for a system under test; generating a metamodel based on the requirements and/or specifications; generating test cases based on the metamodel; prioritizing said test cases based on hazards associated with said test cases; executing one or more of said prioritized test cases; and obtaining a verdict for each of said one or more prioritized test cases.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.