Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

A test controller interfacing between a master computing device and slave computing devices includes a processor configured to launch a master application on the master computing device and a slave application to be tested on each respective slave computing device, with each slave application being the same as the master application. The processor is also configured to receive from the master computing device an input test command along with a test result based on execution of the input test command by the master application, and transmit the received input test command to each slave computing device. In addition, the processor is configured to receive a respective test result from each slave computing device based on execution of the received input test command, and compare each respective test result from the slave computing devices to the test result from the master computing device.

A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

A memory device includes a load generator and a memory controller. The load generator outputs loads for first accesses directed to a memory, irrespective of attributes and characteristics of master devices. The load generator outputs the loads at a constant bandwidth without a change in a bandwidth for outputting the loads. The memory controller receives the loads from the load generator, or receives requests for second accesses directed to the memory from the master devices through a bus. The memory controllers processes the loads such that operations associated with the first accesses are performed in the memory, or processes the requests such that operations associated with the second accesses are performed in the memory. The memory controller processes the loads in a manner which is identical to a manner of processing the requests.

An aircraft annunciator (illuminated switch or indicator) includes, within a housing sized to fit in the panel cutout for a single pushbutton aviation switch, a bus converter to interface with a multiplexed ARINC serial data bus, in order to monitor a remote item of equipment such as an ADS-B transponder. The annunciator is coupled by selected pins to receive data words from the multiplexed ARINC serial data bus. A watchdog timer is continuously reset by valid messages from the transponder, logically ORed with the power supply as well as external analog fault signals in order to generate an output controlling illumination of an FAA-mandated ADS-B FAIL legend on the annunciator.

Systems and methods are provided that may be implemented to detect impaired flow of cooling air within a chassis enclosure of an information handling system during system operation, and to implement a diagnostic or system boot mode to reverse direction of cooling air flow through the chassis enclosure after such detection of impeded cooling air flow so as to remove any dust or other accumulated debris that is causing the impeded cooling air flow.

Systems and methods are provided that may be implemented to detect impaired flow of cooling air within a chassis enclosure of an information handling system during system operation, and to implement a diagnostic or system boot mode to reverse direction of cooling air flow through the chassis enclosure after such detection of impeded cooling air flow so as to remove any dust or other accumulated debris that is causing the impeded cooling air flow.

An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.

Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.