A system for monitoring of integrity of a communication bus includes a communication bus cooperating with at least one transmitter configured to generate and transmit a signal on communication bus. At least one receiver is configured to receive a signal generated by the transmitter and transmitted on communication bus. The receiver is further configured to receive the transmitted signal as well as any reflected signals arising from non-impedance matched section in communication bus and wherein a time difference between transmitted pulse width and received pulse width indicates a distance between the non-impedance matched section and the transmitter on the communication bus.

A test information management device manages test information relating to a test carried out by receiving a test signal output from a first device in a second device. The test information management device includes a linker configured to link together first information including information representing an output state of the test signal in the first device and second information including image information representing reception results of the test signal in the second device using at least one of identification information for identifying the first device or the second device and times at which the first information and the second information are generated.

A test information management device manages test information relating to a test carried out by receiving a test signal output from a first device in a second device. The test information management device includes a linker configured to link together first information including information representing an output state of the test signal in the first device and second information including image information representing reception results of the test signal in the second device using at least one of identification information for identifying the first device or the second device and times at which the first information and the second information are generated.

An evaluation system includes a process execution module that executes an operation in accordance with a safety program, a setting module that receives an evaluation condition, a first determination module that changes the value of the input signal to be evaluated, from a first input value which is an initial value to a second input value, and determines whether a first output value of the output signal to be evaluated which is determined by the process execution module is identical to the expected output value, a second determination module that restores the value of the input signal to be evaluated, from the second input value to the first input value, and determines whether a second output value of the output signal to be evaluated which is determined by the process execution module is identical to the first output value, and an output module that outputs a determination result.

Embodiments of information handling systems (IHSs) and computer-implemented methods are provided herein for testing system memory (or another volatile memory component) of an IHS. In the disclosed embodiments, memory testing is performed automatically: (a) during the pre-boot phase each time a new page of memory is allocated for the first time after a system boot, and (b) during OS runtime each time a read command is received and/or an event is detected. By proactively testing each page of memory, as the page is allocated but before information is stored therein, the systems and methods disclosed herein prevent “bad” memory pages from being used.

Embodiments of information handling systems (IHSs) and computer-implemented methods are provided herein for testing system memory (or another volatile memory component) of an IHS. In the disclosed embodiments, memory testing is performed automatically: (a) during the pre-boot phase each time a new page of memory is allocated for the first time after a system boot, and (b) during OS runtime each time a read command is received and/or an event is detected. By proactively testing each page of memory, as the page is allocated but before information is stored therein, the systems and methods disclosed herein prevent “bad” memory pages from being used.

Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.

Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.

Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.

The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.