Patent classifications
G06F11/3461
Systems and methods for modeling memory access behavior and memory traffic timing behavior
Systems and methods for modeling memory access behavior and memory traffic timing behavior are disclosed. According to an aspect, a method includes receiving data indicative of memory access behavior resulting from instructions executed on a processor. The method also includes determining a statistical profile of the memory access behavior, the profile including tuple statistics of memory access behavior. Further, the method includes generating a clone of the executed instructions based on the statistical profile for use in simulating the memory access behavior.
Estimating service resource consumption based on response time
Implementations of the present disclosure provide computer-implemented methods including defining a workload comprising a plurality of service requests, each service request corresponding to a class of a plurality of classes, applying the workload to a computer system that receives and processes service requests, measuring a response time of the computer system for each request of the workload, estimating a mean service demand for each class based on the response times and a base queuing model that represents the computer system, and generating the queuing model based on the mean service demands and characteristics of the workload.
Hardware In Loop Testing and Generation of Latency Profiles for Use in Simulation
Systems, methods, tangible non-transitory computer-readable media, and devices associated with testing, simulation, or operation of an autonomous device including an autonomous vehicle are provided. For example, a service entity computing system can perform operations including obtaining operating software data associated with operating software of the autonomous vehicle. Log data associated with one or more real-world scenarios can also be obtained. One or more first simulations of the operating software can be performed based on the one or more real-world scenarios. A latency distribution profile associated with the operating software can be generated based on the one or more first simulations. One or more second simulations of the operating software can be performed based on the latency distribution profile and one or more artificially generated scenarios. Furthermore, a real-world behavior of the autonomous vehicle can be predicted based on the one or more second simulations.
LOAD TESTING
Examples relate to load testing. The examples disclosed herein enable obtaining lines of code that are recorded as an application is executed in a client computing device, the lines of code being recorded in chronological order of the execution; determining whether a dependency on at least one variable exists in individual lines of the lines of code; in response to determining that the dependency exists, storing the dependency in a data storage; identifying, from the lines of code, a line of code including a network call statement that calls a called variable; and eliminating a first subset of the lines of code based on the called variable and dependencies stored in the data storage, wherein a second subset of the lines of code that remain after the elimination comprises user-entered parameter data.
Architecture agnostic replay verfication
According to aspects of the disclosure a method is provided, comprising: generating a live execution trace log corresponding to a live execution of a computer program, the live execution being performed by using both hardware emulation and hardware acceleration; generating a first trace entry corresponding to a replay execution of the computer program, the replay execution being performed by using hardware emulation without hardware acceleration, the replay execution being performed based on a set of events that are recorded during the live execution of the computer program; detecting whether the first trace entry is valid based on the live execution trace log; and in response to detecting that the first trace entry is not valid, transitioning into a safe state.
Trace data
A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.
Hardware in loop testing and generation of latency profiles for use in simulation
Systems, methods, tangible non-transitory computer-readable media, and devices associated with testing, simulation, or operation of an autonomous device including an autonomous vehicle are provided. For example, a service entity computing system can perform operations including obtaining operating software data associated with operating software of the autonomous vehicle. Log data associated with one or more real-world scenarios can also be obtained. One or more first simulations of the operating software can be performed based on the one or more real-world scenarios. A latency distribution profile associated with the operating software can be generated based on the one or more first simulations. One or more second simulations of the operating software can be performed based on the latency distribution profile and one or more artificially generated scenarios. Furthermore, a real-world behavior of the autonomous vehicle can be predicted based on the one or more second simulations.
Apparatus, method, and non-transitory computer-readable medium for analyzing trace information
The present disclosure provides an apparatus for analyzing trace information. The apparatus includes one or more storage devices that store a set of instructions, and one or more processors. The one or more processors are configured to execute the set of instructions to cause the apparatus to: obtain, from servers, processor instruction traces corresponding to workloads performed by the servers; generate address traces based on the processor instruction traces; and perform a workload analysis in accordance with the address traces to model resource demands of the workloads.
Information processing apparatus, computer-readable recording medium storing program, and information processing method
An information processing apparatus includes: a memory; and a processor coupled to the memory and the processor configured to calculate shortening rates by comparing execution times for each of a plurality of functions in a case where an evaluation target program is executed in an execution environment with execution times for each of the plurality of functions in a case where the evaluation target program is executed in a simulation environment, and generate a simulation program to be used in the simulation environment based on the calculated shortening rates and the evaluation target program.
Application topology graph for representing uninstrumented objects in a microservices-based architecture
A method of rendering a graphical user interface (GUI) comprising an application topology graph for a microservice architecture comprises generating a plurality of traces from a first plurality of spans generated by instrumented services in the architecture and generating generate a second plurality of spans for uninstrumented services using information extracted from the first plurality of spans. The method further comprises grouping the second plurality of spans with the plurality of traces. Subsequently, the method comprises traversing the traces and collecting a plurality of span pairs from the plurality of traces, wherein each pair of the span pairs is associated with a call between two services. The method also comprises aggregating information across the plurality of span pairs to reduce duplicative information associated with multiple occurrences of a same span pair from the plurality of span pairs. Finally, the method comprises rendering the application topology graph using the aggregated information.