Methods and devices for testing graphics hardware may include reading content of a selected capture file from a plurality of capture files. The methods and devices may include transferring content from the selected capture file to an emulator memory of an emulator separate from the computer device. The methods and devices may include executing at least one pseudo central processing unit (pseudo CPU) operation to coordinate the execution of work on a graphics processing unit (GPU) of the emulator using the content from the selected capture file to test the GPU. The methods and devices may include receiving and store rendered image content from the emulator when the work is completed.

The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further configured to recompute the time compression using programmable circuitry disposed in the hardware emulation system and without stopping the hardware emulation system. Such circuitry may be disposed in a single programmable device disposed in the hardware emulation system or a multitude of programmable devices disposed in the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

An emulator handles problematic target code blocks by evaluating target system code for problematic target code blocks and bypassing translation of such blocks, in some cases selecting alternative host code for a problematic block. Non-problematic portions of the target system code are translated into corresponding portions of host system code, which are inserted into an execution stream. Alternative host system code may also be inserted into the execution stream.

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

Embodiments include herein are directed towards a system and method for glitch debugging in an electronic design. Embodiments may include receiving, using a processor, the electronic design and performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design. If a glitch is identified, embodiments may further include causing a generation of a graphical glitch debugger display. Embodiments may include receiving an edit to the electronic design and re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present.

A touch detector with a code debugger is provided. The touch detector can include a base, a PCBA with a base-side of the PCBA mounted to the base, a frame mounted to a frame-side of the PCBA, and a debugging device mounted on, coupled to, or soldered to the PCBA for debugging other components soldered to the PCBA. The debugging device can be externally accessible to a user when the base, the PCBA, and the frame are mounted together. The touch detector can also include a battery and/or a USB port, each of which can be externally accessible to the user when the base, the PCBA, and the frame are mounted together.

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2. Pages of stored values from the memory address space of the target apparatus 2 may be cached within the emulation.

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Techniques for using emulation to disassociate verification from stimulus in functional test are described. In one approach, a computer stores first data representing an initial state of an application and second data representing the same initial state of a model application, wherein the model application models expected behavior of the application. The computer selects actions for the application to perform and causes both the application and the model application to perform the actions. The computer updates the first and second data to represent the state of both the application and the model application after performing the actions. The computer then compares the first and second data to determine whether both refer to the same state. In response to a determination that the first data and the second data do not refer to the same state, the computer stores data indicating a test failure.