A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

A method, apparatus, and virtual computer system for testing application software. A first operating system of a first operating type is run on a first processor of a first processor type in a physical computer system. A virtual machine that emulates a second processor of a second processor type is run on the first processor. A second operating system of a second operating type is run on the virtual machine with the virtual machine running on the first processor. The first processor running the first operating system and the virtual machine running the second operating system together form the virtual computer system. A tool qualifier module performs verification of an application testing tool on the virtual machine using tool qualification data to qualify the application testing tool before the application testing tool is run using the second operating system on the virtual machine to test an application program.

Collecting runtime virtual machine external state for an application running in an application runtime virtual machine, for use in emulation of the application. A method includes identifying application bytecode for which runtime virtual machine external state is to be collected. The method further includes executing machine code generated from the bytecode to generate the runtime virtual machine external state. The method further includes collecting the runtime virtual machine external state. The method further includes storing the runtime virtual machine external state for use in emulating the application.

Emulating execution of second code of a second instruction set architecture (ISA) using a trace of execution of first code of a first ISA. The stores data of an input that was consumed by the first code when executing on the first ISA. It is determined that the stored data of the input is usable as an input to the second code. Difference(s) in location/size/format of the stored data as used by the first code, compared to a location/size/format expected by the second code, is identified. Based on the identified difference(s), transformation(s) are determined that would enable the second code to access and consume the stored data when being emulated on the second ISA. Execution of the second code is emulated on the second ISA using the stored data, including projecting the transformation(s) to enable the second code to access and consume the stored data.

Mapping input locations to enable execution of second executable code using trace data gathered during execution of first executable code. A trace of a prior execution of the first code, and the second code, are accessed. The trace stores data of an input that was consumed by first executable instructions of the first code. It is determined that the stored data of the input is usable as an input to second executable instructions of the second code. A difference in how the first instructions accessed the input during recording, as compared to how the second instructions expect to access input, is identified. Based on the identified difference, a location transformation is determined that would enable the second instructions to access the stored data. Execution of the second instructions is emulated using the stored data, including projecting the location transformation to enable the second instructions to access the stored data.

An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a platform neutral debug station. The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit (SDC) that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.

Diagnosing applications that use hardware acceleration can include emulating, using a processor, a kernel designated for hardware acceleration by executing a device program binary implementing a register transfer level simulator for the kernel. The device program binary is executed in coordination with a host binary and a static circuitry binary. During the emulation, error conditions may be detected using diagnostic program code of the static circuitry binary. The error conditions may relate to memory access violations or kernel deadlocks. A notification of error conditions may be output.