Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

A version management method includes the following steps: selecting a master branch; receiving bug information, wherein the bug information includes the bug state; and setting the bug state to a working state after receiving a confirmation assignment message corresponding to the bug information; in response to setting the bug state to the working state, generating a branch corresponding to the bug information based on the master branch, and merging modified code of the branch to a candidate branch; and in response to the release time arriving, merging the candidate branch to the master branch, and setting the bug state to a verification state.

Disclosed herein are a method for automated fuzzing for an IoT device based on automated reset and an apparatus using the same. The method includes loading, by the apparatus, a fuzzing agent into an IoT device based on firmware; monitoring, by the apparatus, the status of processing of fuzzing input by the IoT device based on the fuzzing agent; collecting, by the apparatus, fuzzing data corresponding to occurrence of a crash based on hooking using the fuzzing agent when the crash occurs in the IoT device; and resetting, by the apparatus, the IoT device based on the fuzzing agent.

The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers. The present disclosure can realize rapid configuration and control of debug event signal transmission, and at the same time lower power consumption of a debug circuit.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

Systems and methods for delta state tracking for event stream analysis. Events at a device are tracked and stored locally or forwarded to a server. The events collectively form an event stream. When an event of interest occurs, the precise configuration of a device at the time of the event of interest can be determined by applying the event stream in chronological or reverse chronological order to a snapshot of the device's configuration. Thus, the snapshot can be taken at any time. Tracking the deltas to the device's configuration enables the precise configuration at the time of the event of interest to be determined.

A computer-implemented method for debugging an executable control flow graph that specifies control flow among a plurality of functional modules, with the control flow being represented as transitions among the plurality of functional modules, the computer-implemented method including: specifying a position in the executable control flow graph at which execution of the executable control flow graph is to be interrupted; wherein the specified position represents a transition to a given functional module, a transition to a state in which contents of the given functional module are executed or a transition from the given functional module; starting execution of the executable control flow graph in an execution environment; and at a point of execution representing the specified position, interrupting execution of the executable control flow graph; and providing data representing one or more attributes of the execution environment in which the given functional module is being executed.

The present application discloses an on-chip code breakpoint debugging method, an on-chip processor, and a chip breakpoint debugging system. The on-chip processor starts and executes an on-chip code, and an output function is set at a breakpoint position of the on-chip code. The on-chip processor obtains output information output by the output function, and stores the output information into an off-chip memory. In one embodiment, according to the output information, output by the output function and stored in the off-chip memory, the on-chip processor can obtain execution conditions of the breakpoints of the on-chip code in real time, achieve the purpose of debugging multiple breakpoints in the on-chip code concurrently, and improve debugging efficiency.

A processor comprising at least one processing module, each processing module comprising: an execution pipeline; memory; an instruction fetch unit comprising operable to switch between an operational mode and a debugging mode, the instruction fetch unit being configured so as, when in the operational mode, to fetch machine code instructions from the memory into the execution pipeline to be executed; and a debug interface for connecting to a debug adapter. The debug interface comprises a debug instruction register enabling the debug adapter to write a machine code instruction to the debug instruction register, and wherein the instruction fetch unit is configured so as, when in the debug mode, to fetch instructions from the debug instruction register into the pipeline instead of from the memory.

An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.