The application discloses a debugging method for a noise elimination algorithm, an apparatus and an electronic device, which relate to the technical fields of voice, automatic driving and intelligent transportation. An implementation scheme is: when the noise elimination algorithm is debugged, acquiring multiple voice control signals from a vehicle to be debugged, modifying a weight of a configuration parameter of the noise elimination algorithm in a digital signal processing to obtain an updated noise elimination algorithm; then adopting the updated noise elimination algorithm to perform noise elimination processing on the multiple voice control signals; if control results of noise-eliminated voice control signals on the vehicle to be debugged do not meet a preset condition, continuing to modify the weight of the configuration parameter until the preset condition is met, and then sending a noise elimination algorithm that meets the preset condition to the vehicle to be debugged.

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

Provided herein may be a debug device, a debug system, and a debug method. The debug device may include a communicator coupled to a debug interface of a storage device, an interrupt signal generator configured to, when a request to measure an operation time for an instruction is received, output an interrupt signal for controlling an interrupt operation to be performed by the storage device, through the communicator, a tick count detector configured to acquire first tick counts corresponding to a start time point and an end time point of the interrupt operation and acquire second tick counts corresponding to a start time point and an end time point of the instruction, through the communicator, and a calibrator configured to determine the operation time using the first tick counts and the second tick counts.

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

An application debugging method includes an interaction sub-system receiving identifiers of a plurality of application sub-modules that are input or selected by a user, creating debug sessions that are in a one-to-one correspondence with the plurality of application sub-modules, and then generating a plurality of debugging request messages based on the plurality of debug sessions. Each debugging request message is routed by the routing sub-system to an agent of an application sub-module requested to be debugged, to request debugging of a code block of the corresponding application sub-module.

An exemplary method is disclosed that facilitate the on-demand creation of an exemplary instrumented network device in a cloud infrastructure, remote server, evaluation platform, or customized testing server and to form a stack between the instrumented network device as a debug network device and a target network device. The control plane of the target network device then switches over, via a switchover operation, to the control plane of the debug network device, while the data-plane of the target network device continues to operate. Once switched over, the instrumentation (e.g., hardware or software) of the control plane or debug network device facilitates the debug, optimization, profile, and/or recovery of the physical network device, even in a live network.

The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.