A connection can be made to a processing element of a remotely deployed and live streaming application executed by a first data processing system, the processing element containing at least one operator that processes at least one tuple. As the live streaming application is executed, without slowing or modifying data flow of the live streaming application execution to client devices, a copy of the tuple and a memory dump of state data for a state of the operator can be received, and the tuple can be tracked through a call graph. The state data can be loaded into a local instance of the operator loaded into a debugger. At least a portion of the call graph can be presented to a user, and a flow of the tuple through the call graph based on the state data for the operator can be indicated.

Embodiments of the present invention provide a system, method, and program product for an abnormal timing breakpoints. A computer determines a code section, wherein the code section is part of computer code edited by a user. The computer determines an expected timeframe and an expected count for the code section, wherein the expected timeframe represents a predicted time to execute the code section, and wherein the expected execution count represent a predicted number of executions of the code section. The computer determines that an execution of the code section is abnormal based on one or more of: determining a current execution time is greater than the expected timeframe, and determining a current execution count is greater than the expected count. The computer halting the execution of the code section based on determining that the execution of the code section is abnormal and displays the abnormal code section.

Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of predetermined instructions within the sequence. The instruction sequence includes at least one branch-future instruction that effectively turns an instruction identified by the branch-future instruction into a branch, and in particular causes the processing circuitry to branch to a target address identified by the branch-future instruction when that identified instruction is encountered within the instruction sequence. A branch control cache is used to store branch control information derived from the branch-future instruction, and the trace generation circuitry is arranged to detect, based on that branch control information, when the identified instruction has been encountered by the processing circuitry, and upon such detection to then issue within the trace stream a trace element to indicate that a branch to the target address has occurred. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch-future instructions.

Systems and methods for delta state tracking for event stream analysis. Events at a device are tracked and stored locally or forwarded to a server. The events collectively form an event stream. When an event of interest occurs, the precise configuration of a device at the time of the event of interest can be determined by applying the event stream in chronological or reverse chronological order to a snapshot of the device's configuration. Thus, the snapshot can be taken at any time. Tracking the deltas to the device's configuration enables the precise configuration at the time of the event of interest to be determined.

A method for processing data, includes: acquiring data packets having respective serial numbers and transmitted between a first microcontroller unit (MCU) and a second MCU of a smart device, the second MCU being provided in a Wireless Fidelity (Wi-Fi) module of the smart device; and processing and displaying the acquired data packets based on the respective serial numbers so as to debug the second MCU.

According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.

An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being