An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

An apparatus to facilitate matchmaking-based enhanced debugging for microservices architectures is disclosed. The apparatus includes one or more processors to: detect, by an anomaly detector in a sidecar of a microservice hosted by a container, an anomaly in telemetry data generated by the microservice, the microservice hosted in a container executed by the processor and part of a service of an application; enable, by an enhanced debug and trace component of the sidecar, a debug mode in the microservice, the debug mode based on a type of the anomaly; collect, by the enhanced debug and trace component, a target set of data points generated by the microservice; and process, by the enhanced debug and trace component, the target set of data points with a matchmaking process to generate a timestamp and a tag for a context for each data point of the target set of data points.

In accordance with some embodiments, a method is performed at a device with one or more processors, non-transitory memory, a display, and an input device. The method includes receiving, from an application, application output data and accessibility metadata associated with user interface elements of a user interface of the application, wherein the accessibility metadata can be used by accessibility modules to identify, describe, or enable interaction with the user interface elements. The method includes comparing the application output data to the accessibility metadata. The method include determining, based on comparing the application output data to the accessibility metadata, that a particular user interface element of the user interface of the application lacks accurate corresponding accessibility metadata. The method includes displaying, on the display, a report including an indication that the particular user interface element lacks accurate corresponding accessibility metadata.

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.

A software-development tool can present telemetry data with associated source code. For example, a computing device can identify, by a text editor, source code of a software application that is associated with telemetry data of performance metrics associated with running the source code. The computing device can display, by the text editor, an icon with the source code. The icon can indicate the source code is associated with the telemetry data. The computing device can receive an interaction with the icon. In response to receiving the interaction, the computing device can retrieve, by the text editor, the telemetry data from a telemetry-data repository for display in the text editor.

A client device instantiates an isolator application. A request to instantiate a remote application in a server device is sent by the isolator application instance. The isolator application instance receives, from the remote application instance, draw commands and position information that correspond to the draw commands. The isolator application instance renders one or more portions of output based on the draw commands and the position information.

A communication device intended to be connected to a debugging port of a first microcontroller, the communication device including a second microcontroller connected to a first wireless communication unit and intended to be connected to said debugging port, the first wireless communication unit being capable of receiving a request over a wireless communication link transmitted by a user interface device, the second microcontroller being capable of authenticating the user interface device, of determining, in the case where the user interface device is authenticated, whether the request is authorized for said authenticated user interface device, and of transmitting the request to the debugging port only if the request is authorized.

A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

According to one embodiment, a memory system includes a first memory and a controller. The controller includes first and second decoders, first and second circuits, a register, and a switching circuit. The first and second decoders decode first and second commands respectively, which include first and second addresses respectively. The first and second circuits access the first memory using the first and second addresses respectively. A value stored in the register is changeable by a host. The switching circuit switches between the first and second circuits to access the first memory according to the value in the register.