Disclosed is an apparatus for verifying a bootloader of an electronic control unit and a method thereof. The apparatus for verifying a bootloader of an electronic control unit includes storage that stores a message authentication code (MAC) for the bootloader of the electronic control unit; and a controller that verifies a digital signature of firmware received from the electronic control unit and when a result of verification for the digital signature is normal, changes the MAC for the bootloader of the electronic control unit.

A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.

A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region. The peripheral circuit region includes second metal pads, a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device, a debugging information generator that generates debugging information based on the stored control signals and the stored data signal, and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.

In some aspects, a debugging application can obtain log data from a target device. The log data can be generated from the execution of object code by the target device. The object code can be generated from assembly code for the target device. For each of multiple program counter entries in the log data, the debugging application can identify a correspondence between the program counter entry and a respective portion of the assembly code and simulate a respective operation performed by the execution of the object code. The simulated operation corresponds to the program counter entry. Simulating the execution can include configuring a display device to display a visual indicator for the portion of the assembly code that caused a given operation. The visual indicator is displayed based on the identified correspondence between a portion of the assembly code and a program counter entry from the log data.

Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.

A method and apparatus for collecting debug and crash information are described. In one embodiment, a system comprises one or more compute engines an external interface; a non-volatile memory coupled to the external interface and operable to store captured information, wherein the captured information comprises one or both of debug information and crash information; a first trace aggregator coupled to the non-volatile memory and the one or more compute engines to capture the one or both of debug information and crash information from at least one of the one or more compute engines in response to a crash of the system; and a controller, coupled to the non-volatile memory and the first trace aggregator, to cause captured information to be sent from the first trace aggregator to the non-volatile memory and to subsequently control transfer of the captured information stored in the non-volatile memory to the external interface.

In one embodiment, a method includes: in response to identifying an error in a device of a computing environment coupled to a host system of the computing environment via a serial link, sending, from a requester, a debug type messaging (DTM) request towards the device via a sideband portion of the serial link, the requester in-situ to the computing environment; and receiving, in the requester, a DTM response to the DTM request, the DTM response including status information of the device, via the sideband portion of the serial link. Other embodiments are described and claimed.

A processor or system includes a processor core to execute a set of instructions to determine that a memory encryption mode is enabled. The memory encryption mode is to cause data stored to memory to be encrypted and data retrieved from the memory to be decrypted. The processor core is further to determine that a debug mode has been enabled and, responsive to a determination that the debug mode has been enabled, generate a second encryption key different than a first encryption key employed before reboot of a computing system. The processor core is further to transmit the second encryption key to a cryptographic engine for use in encryption and decryption of the data according to the memory encryption mode.

An application access control method and apparatus includes acquiring a graphic input by a user; generating an access strategy graphic according to the graphic, where the access strategy graphic indicates an access rule of whether at least two applications are allowed to access each other; converting the access strategy graphic into an access control strategy that can be identified by a system, where the access control strategy is used to indicate whether applications are allowed to access each other; and controlling access between the at least two applications according to the access control strategy. A graphic input by a user is acquired, and an access strategy graphic formed by the graphic is converted into an access control strategy that can be identified by a system, so as to control application access according to the access control strategy.