An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without breaking the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as hardware logic on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

A process for regenerating a silica-supported depleted alkali metal catalyst is described. The level of alkali metal on the depleted catalyst is at least 0.5 mol % and the silica support is a zero-gel. The process comprises the steps of contacting the silica supported depleted alkali metal catalyst with a solution of a salt of the alkali metal in a solvent system that has a polar organic solvent as the majority component. A re-impregnated catalyst prepared by the process of the invention any comprising a silica zero-gel support and a catalytic metal selected from an alkali metal in the range 0.5-5 mol % on the catalyst, wherein the surface area of the silica support is <180 m.sup.2/g is also described. The invention is applicable to a process for preparing an ethylenically unsaturated acid or ester comprising contacting an alkanoic acid or ester of the formula R.sup.1CH.sub.2COOR.sup.3, with formaldehyde or a suitable source of formaldehyde.

Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. All trace data streams may generate a sync point with this unique identifier. These unique identifiers allow synchronization between multiple trace data streams. When multiple trace data streams are on, it is possible that the data input rate may be higher than the data output rate. If synchronization is lost in such a case, there must be a scheme to resynchronize the streams. This invention is a technique for this needed resynchronization.

An embodiment provides a memory system connectable to a host device. The memory system includes a host interface configured to receive a read command and a write command and a first non-volatile memory. In addition, the memory system includes a debug unit configured to collect debugging information when a processor executes firmware. The debug unit is capable of outputting the debugging information to a buffer area of the host device through the host interface.

A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.

Technologies are provided herein for automated operating system installation. Through the concepts and technologies presented herein, the process of installing multiple operating systems on a system under test (SUT) can be automated and monitored, thereby permitting the unattended installation of the operating systems. Multiple operating systems can be installed and errors detected during the installations can be logged in an automated fashion, thereby reducing the cost of such testing. Errors generated during the automated installation process can be analyzed and utilized to identify and correct errors in a computing system firmware. A device selector for facilitating the automated installation process is also provided.