G06F11/3656

FLASH MEMORY CONTROLLER, DATA PROCESSING SYSTEM WITH FLASH MEMORY CONTROLLER AND METHOD OF OPERATING A FLASH MEMORY CONTROLLER

The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

Serial/parallel control, separate tap, master reset synchronizer for tap domains
09535122 · 2017-01-03 · ·

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Graphical user interface and log analysis tool for analyzing log data to identify errors associated with application execution
12292820 · 2025-05-06 · ·

A system can be provided that can generate a network connection with a computing environment. The computing environment can include development environments that can execute software applications. The system can generate a graphical user interface for display on a display device and detect a selection of a graphical submit element within the graphical user interface by a user. In response to detecting the selection of the graphical submit element, the system can obtain log data from the computing environment. The system can update a first graphical frame to display the log data in its raw format as received from the computing environment and can update a second graphical frame to display a modified version of the log data that highlights operational errors associated with a software application executing in a development environment. The operational errors can be identified by the system analyzing the log data.

SYSTEM FOR FILTERING MEASUREMENT DATA AND FILTERING METHOD THEREOF
20250165369 · 2025-05-22 · ·

A system for filtering measurement data, comprising: a bus adapter, configured to obtain a data source from an Electronic Control Unit (ECU); at least one computer device, comprising a processor, a display communicating with the processor to present a graphical interface, a readable storage medium, a communication bus and communication interface; wherein, the processor, the readable storage medium and the communication interface communicate with the bus adapter via the communication bus; the readable storage medium is configured to store instructions; the processor is configured to, after obtaining the data source, execute the instructions to perform the operations: setting an upstream data flow input port, a downstream data flow output port and a filtering function for each measurement window; connecting the upstream data flow input port of each measurement window to the downstream data flow output port of one measurement window other than the measurement window to form a hierarchical connection.

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICROCONTROLLER UNIT

An example system, e.g., a system on a chip (SoC), includes first and second domains having first and second processors, respectively. The second processor is part of a processing subsystem in the second domain. The first processor provides an instruction to the second processor, which executes the instruction to configure the processing subsystem to operate in a mode specified by the instruction. In response to the processing subsystem being configured to operate in the specified mode, isolation circuitry of the system is configured to provide a level of isolation between the first domain and the second domain based on the specified mode.

DEBUGGING TOOLS FOR CLUSTER FILE SYSTEM SERVICEABILITY
20250208989 · 2025-06-26 ·

A single multi-container service pod that provides a centralized cluster-aware debugger and a centralized set of debugging tools where the service pod contains one or more containers for applications executed by the cluster system. Each debugging tool of the set is associated with a respective application, such as a dump utility, a connection checker, and a log search utility. A vendor providing support for the cluster network, executes a corresponding debugging tool of the set of debugging tools to address a problem encountered by a node executing an application. Debugging the problem from the service pod impacts a debugged application on the other pods, and the service pod can trigger the debugging tools on other applications on the nodes.

Computer-implemented method for assisting a user in debugging roles in a software system
12346465 · 2025-07-01 · ·

The disclosed includes the steps of: providing a predetermined set of recorded roles whereby the user associated with the recorded roles contains at least a permission allowing the user to get access to resources of a technical system during execution of the software system on the technical system, computing a plurality of combinations of intersection sets based on the predetermined recorded roles if the at least one permission of the first and the at least one permission of the second further role overlaps, creating a Venn diagram with a first and second graphical display element representing a first role and a second further role respectively; and displaying the Venn diagram for use by a user in debugging the roles in the software system, wherein the first and the second display element is placed in a visual representation to give the user the cue for each of the intersection sets.

Processor with debug pipeline

A processor includes execution circuitry, within an execution power domain, to process an instruction; and a debug system, within a separate debug power domain, to selectively operate to perform debugging operations on the processor. The processor further includes power control circuitry coupled to the debug system; and detection circuitry coupled to the power control circuitry. The power control circuitry causes power to be supplied to the debug system when the detection circuitry indicates that a debug tool is coupled to the processor, and disables power supply to the debug system when the detection circuitry indicates that the debug tool is not coupled to the processor.

GRAPHICAL USER INTERFACE AND LOG ANALYSIS TOOL FOR ANALYZING LOG DATA TO IDENTIFY ERRORS ASSOCIATED WITH APPLICATION EXECUTION
20250231861 · 2025-07-17 · ·

A system can be provided that can generate a network connection with a computing environment. The computing environment can include development environments that can execute software applications. The system can generate a graphical user interface for display on a display device and detect a selection of a graphical submit element within the graphical user interface by a user. In response to detecting the selection of the graphical submit element, the system can obtain log data from the computing environment. The system can update a first graphical frame to display the log data in its raw format as received from the computing environment and can update a second graphical frame to display a modified version of the log data that highlights operational errors associated with a software application executing in a development environment. The operational errors can be identified by the system analyzing the log data.

PROCESSOR ERROR DETECTION WITH ASSERTION REGISTERS
20250245085 · 2025-07-31 · ·

Techniques for debugging errors in a processor are disclosed. One or more processors are accessed. Each processor within the one or more processors includes a set of assertion registers. A processor within the one or more processors executes one or more instructions. An assertion logic detects an error condition in the processor. The detecting occurs during the executing. The error condition is recorded. The recording is based on one or more bits in the set of assertion registers. A hardware interface reads the one or more bits in the set of assertion registers. The one or more bits indicate the error condition to the hardware interface. The executing includes a communication protocol between the processor and a slave device. The error condition comprises an incorrect value in a credit buffer. The credit buffer controls a number of transactions allowed between the processor and the slave device.