A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.

A memory device includes a plurality of pages. Each page includes a data region configured to store data, an error correction code (ECC) region configured to store ECC data that is used to detect and correct one or more errors occurring in the data stored in the data region, and a metadata region configured to store a write count of a corresponding page.

One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

The present application discloses a memory control method, a controller, a chip and an electronic device, and relates to the field of control technology. A specific implementation solution is: obtaining first address information of an access to the memory performed by the processor within a first time window; determining, according to the first address information and an address jump relationship, a target slice of the memory that is to be accessed by the processor within a second time window; and controlling the target slice in the memory to be turned on and controlling a slice other than the target slice in the memory to be turned off within the second time window. Through the above-mentioned process, each slice is dynamically turned on and off according to the actual situation of memory access, thereby reducing the power consumption of the memory to the maximum extent.

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

A memory card controller coupled to a host device includes a processing circuit which is used for reading card specific data from a flash memory of a memory card to store the card specific data in a register wherein a multiply parameter and a basic capacity are marked in the card specific data and used for sending the card specific data to the host device to make the host device calculate a maximum capacity of the memory card according to the multiply parameter and the basic capacity marked in the card specific data.

Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.