In one embodiment, an apparatus includes a processor comprising an address translation cache (ATC); a shared work queue (SWQ) associated with the ATC, and a port to couple to a host processor over a Peripheral Component Interconnect Express (PCIe)-based link. The apparatus also includes circuitry to receive address translation information from a memory management unit of the host processor that includes virtual memory address to physical memory address translations, store the address translation information in the ATC, receive an invalidation command from the host processor indicating an invalidation of address translation information stored in the ATC, modify the address translation information in the ATC based on the invalidation command, and store completion data in a memory location indicated by the invalidation command.

In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

The present disclosure provides methods, apparatuses, and servers for cache-coherence. In some embodiments, an apparatus includes a plurality of compute express link (CXL) devices, and a switch. Each CXL device of the plurality of CXL devices includes a memory in which a portion of the memory is allocated as a cache buffer, to which different cache eviction policies are allocated. The different cache eviction policies are modified according to a cache hit ratio of the cache buffer. The switch is configured to connect the plurality of CXL devices to each other.

The present disclosure provides methods, apparatuses, and servers for cache-coherence. In some embodiments, an apparatus includes a plurality of compute express link (CXL) devices, and a switch. Each CXL device of the plurality of CXL devices includes a memory in which a portion of the memory is allocated as a cache buffer, to which different cache eviction policies are allocated. The different cache eviction policies are modified according to a cache hit ratio of the cache buffer. The switch is configured to connect the plurality of CXL devices to each other.

Systems and methods for high availability distributed data storage are provided. In embodiments, a method includes: receiving, by a remote direct memory access (RDMA) switch operatively coupled to a computing device, a request to access a page of a database; determining, by the RDMA switch, a validation state of the page; determining, by the RDMA switch, a status of the page; updating, by the RDMA switch, the status of the page based on the validation state and the request; and reporting, by the RDMA switch, the validation state.

Systems and methods for high availability distributed data storage are provided. In embodiments, a method includes: receiving, by a remote direct memory access (RDMA) switch operatively coupled to a computing device, a request to access a page of a database; determining, by the RDMA switch, a validation state of the page; determining, by the RDMA switch, a status of the page; updating, by the RDMA switch, the status of the page based on the validation state and the request; and reporting, by the RDMA switch, the validation state.

Disclosed is a data set and node cache-based scheduling method, which includes: obtaining storage resource information of each host node; in response to receiving a training task, obtaining operation information of the training task, and according to the operation information and the storage resource information, screening host nodes that satisfy a space required by the training task; in response to no host node satisfying the space required by the training task, scoring each host node according to the storage resource information; according to scoring results, selecting, from among all of the host nodes, a host node to be executed that is used to execute the training task; and obtaining and deleting an obsolete data set cache in the host node to be executed, and executing the training task in the host node to be executed.

Disclosed is a data set and node cache-based scheduling method, which includes: obtaining storage resource information of each host node; in response to receiving a training task, obtaining operation information of the training task, and according to the operation information and the storage resource information, screening host nodes that satisfy a space required by the training task; in response to no host node satisfying the space required by the training task, scoring each host node according to the storage resource information; according to scoring results, selecting, from among all of the host nodes, a host node to be executed that is used to execute the training task; and obtaining and deleting an obsolete data set cache in the host node to be executed, and executing the training task in the host node to be executed.

A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.