A device for providing a localized executable functions platform to generate information for control systems. The device may comprise an I/O interface configured to communicate with the control systems, a memory configured to store a set of executable functions, and an executable functions platform configured to receive an initialization, determine an executable function needed to obtain information pertaining to a control system, access the executable function from the memory, run the executable function using input data for the control system, obtain the information pertaining to the control system in response to running the executable function, and provide the information pertaining to the control system.

Provided is a storage system in which a plurality of storage controllers communicate with each other and an identifier of each storage controller is determined. The storage system includes a plurality of controllers that receive and process an input and output request specifying any of a plurality of volumes from an external device, and a plurality of switches each having a plurality of ports. The plurality of controllers are connected in parallel to the plurality of switches and communicate with each other via the plurality of switches. Each of the plurality of controllers acquires a plurality of port identifiers identifying a plurality of connected ports from the connected switches, and determines a controller identifier in the storage system based on the acquired plurality of port identifiers.

The present invention is directed to a system and method that utilizes a central repository for storing and sharing Thing Description (TD) Documents with USB extensions that correspond to specific USB I/O schema. A Network Interface Module uses the USB I/O vendor and product identifications to query the central repository and download the appropriate Thing Description (TD) document for the specific USB I/O device. The Network Interface Module parses the TD document and builds the appropriate Web of Things (WoT) data architecture that establishes the interface between the network and the USB I/O device thereby allowing the USB I/O device to become an IoT device.

Disclosed are a method and apparatus for writing data from an Advanced eXtensible Interface (AXI) bus to an On-chip Peripheral Bus (OPB), a method and apparatus for reading the data from the AXI bus to the OPB, an electronic device and a non-transitory computer readable storage medium. The method for writing the data includes the following steps: receiving AXI write data sent by the AXI bus (S101); storing the AXI write data into an AXI write cache (S102); performing timing conversion from an AXI bus protocol to an OPB protocol on the AXI write data to obtain OPB write data (S103); and exporting the OPB write data from the AXI write cache to the OPB (S104). By applying the method for writing the data, data interaction between the AXI bus and the OPB is completed, the cost is reduced, and the project development efficiency is improved.

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.

A device for supervising ports of an integrated circuit is arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of the integrated circuit. The device comprises address decoding means, access control means, and parity controlling means. The device for supervising ports comprises read-back information means arranged for receiving input from the port and for passing that input to the parity control means and in that the address decoding means, the access control means, the read-back information means and the parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored. The read-back information means reads data and one or more parity bits stored on ports with an address in the range and the parity controlling means performs a parity check on the one or more parity bits stored on the ports.

A method of synchronizing thread execution of a host and one or more coprocessors includes writing by the host of an event command and at least one coprocessor instruction to a FIFO and comparing of the event command with a current event register of the coprocessor until they match, whereupon the FIFO entries are popped and the instructions are forwarded to the coprocessor for execution. A plurality of entry groups can be written to the FIFO, each beginning with an event command. The instructions can direct the coprocessor to exchange data with shared memory and apply its thread to the received data. The processors and shared memory can be linked by a ring-type bus having a controller that performs the comparison, popping, and instruction forwarding. The coprocessor clears the current event register during thread execution, and then writes an event command to the register when processing is complete.

An information processing apparatus includes an interface switching circuit including a first hardware interface to which a first device part is coupled; and a first processor including a second hardware interface, wherein the interface switching circuit is configured to block, when hot-removal of the first device part is detected, a signal path between the first hardware interface and the second hardware interface, and cancel, when diagnosis for a second device part newly hot-inserted in the first hardware interface is completed, the blocking of the signal path in response to a result of the diagnosis, and the first processor is configured to detect presence of the second device part from that the first processor transits from a non-responsive state to a responsible state, and execute an initialization process for the second device part.

A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.