The present technology relates to an information processing device that is adapted to be capable of transmitting/receiving data with smaller amounts of processing and data, and a method, and a program. The information processing device is provided with: a control unit that subjects information related to a collection target user to computation using one or more predetermined functions, and generates collected data on the basis of a result of the computation; and a communication unit that transmits the collected data. The present technology can be applied to a statistical information-sharing system.

A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

According to certain implementations, a motherboard is provided that enables operation as either multiple independent single-processor systems or a single multiple-processor system. In response to a request to configure the motherboard as multiple independent single-processor systems, a control block is implemented for each processor attached to the motherboard, where the control blocks configure the processors to boot and operate independently of each other, and the processors utilize separate motherboard resources. In response to a request to configure the motherboard as multiple independent single-processor systems, a single control block is implemented all processors attached to the motherboard, where the single control block configures all processors to boot and operate in a connected state, and the processors share all motherboard resources.

An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialization signal comprising port initialization data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialization signal comprising the port initialization data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialization signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialization data and the just obtained original one or more parity bits.

Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

In an arrangement of an electrically communicative voltage supply for controlled operation of at least one electrically operable IO-Link device using an electrical DC voltage provided by a voltage supply unit as well as an IO-Link communication interface which is provided for the controlled operation of the at least one IO-Link device and formed with at least one channel, the IO-Link communication interface which is formed with at least one channel and the voltage supply unit form a structural unit and the IO-Link communication interface includes an IO-link master providing a gateway function.

An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

An electronic control system is disclosed for controlling individually controllable elements of an external component. In one embodiment the system may include a state translator subsystem for receiving a state command from an external subsystem. The state translator subsystem may have at least one module for processing the state command and generating operational commands for controlling the elements to achieve a desired state or condition. A programmable calibration command translation layer (PCCTL) subsystem may be included which receives and uses the operational commands to generate granular level commands for controlling the elements. A feedback control layer subsystem may be included which applies the granular level commands to the elements, and further modifies the granular level commands as needed to control the elements in closed loop fashion.