Patent classifications
G06F13/126
ELECTRONIC DEVICE AND DATA TRANSMITTING/RECEIVING METHOD
An electronic device includes a first device, a second device, and a storage area shared by the first device and the second device when performing mailbox communication between the first device and the second device. When transmitting first data from the first device to the second device via the mailbox communication, the first device stores first data in the storage area. The second device, which has stored therein an identifier of a device permitted to transmit data to the second device via the mailbox communication, obtains an identifier of the first device, and compares the obtained identifier to the identifier stored in the second device to determine whether acquisition of the first data from the storage area is permitted. When the acquisition of the first data from the storage area is determined to be permitted, the second device reads the first data from the storage area.
Managing starvation in a distributed arbitration scheme
Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.
System and method for individual addressing
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
Local instantiation of remote peripheral devices
Enhanced apparatuses, systems, and techniques for coupling network-linked peripheral devices into host computing devices is presented. A method includes, over a network interface of a host device, obtaining an indication of a peripheral device available for associating with the host device. Based on the indication, the method includes initiating instantiation of the peripheral device into a Peripheral Component Interconnect Express (PCIe) subsystem of the host device by at least emulating behavior of the peripheral device over the network interface as a PCIe peripheral device coupled locally to the host system.
NETWORK INSTANTIATED PERIPHERAL DEVICES
Enhanced apparatuses, systems, and techniques for coupling network-linked peripheral devices into host computing devices is presented. A method includes, over a network interface of a host device, obtaining an indication of a peripheral device available for associating with the host device. Based on the indication, the method includes initiating instantiation of the peripheral device into a Peripheral Component Interconnect Express (PCIe) subsystem of the host device by at least emulating behavior of the peripheral device over the network interface as a PCIe peripheral device coupled locally to the host system.
Sequencer chaining circuitry
A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
Massively parallel hierarchical control system and method
A system is disclosed for controlling controllable elements of an external component. The system uses a state translator subsystem (STS) which receives a state command from an external subsystem. The STS has at least one module for processing the state command and generating operational commands, in parallel, over a first plurality of channels, to control the elements of the external component. A programmable calibration command translation layer subsystem (PCCTL) uses the operational commands to generate granular level commands for controlling the elements, and to transmit the granular level commands over a second plurality of channels. A subsystem is coupled between the PCCTL and the elements, which receives the commands from the PCCTL and uses the commands to generate final output commands, which are applied in parallel, over a third plurality of channels, to the elements.
Systems and devices for accessing a state machine
A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
System and method for application migration for a dockable device
Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.
CONFIGURING DOCKS
In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.