A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

A virtualized peripheral driver and filter are installed at a kernel level of an Operating System (OS) on a host device. A new peripheral driver is installed on the host device and added to the peripheral device stack within the OS. Events generated from the user level of the OS are pushed through the stack for processing by a newly attached peripheral of the host device using the new peripheral driver. Events produced from the kernel for the peripheral are trapped by the filter when passing up through the stack to the user level of the OS and provided to the virtualized peripheral driver. The virtualized peripheral driver repackages, translates, and formats the events produced from the kernel as OS events expected by the OS for processing and the repacked, translated, and formatted events are processed by the OS.

A user terminal accepts an edition of a program to have a control unit of a basic part perform electronic component control using a library stored in a library storage accessed from a plurality of user terminals in common. The user terminal transmits, to a server system, a command to have the control unit of the basic part perform the electronic component control in accordance with execution of the program. The server system receives a command transmitted from the user terminal, and transmits a command based on the received command to the basic part. The control unit of the basic part performs the electronic component control based on the command transmitted from the server system.

A computer program product may include storage media embodying program instructions executable by a baseboard management controller (BMC) within a compute node to: receive a request to install a central processing unit (CPU) in the compute node; identify a current hardware configuration of the compute node; identify a plurality of available locations within the compute node that are compatible with installation of the CPU; calculate, for each of the identified plurality of available locations, a predicted performance score for the CPU on the basis that the CPU were to be installed in the available location, wherein the predicted performance scores are calculated in response to receiving the request; select a location from among the plurality of available locations that is associated with the greatest performance score for the CPU; and generate user output indicating the selected location where the CPU should be installed.

A gateway apparatus is provided, including: a storage unit storing a plurality of different filter information pieces each including an application target ECU configuration, a filter condition indicating a condition of data allowed to be transferred to the ECU and a filter version, in a manner associated with each other; a selection unit selecting, from among the plurality of different filter information pieces, a filter information piece whose application target ECU configuration corresponds to an ECU configuration of an ECU installed in the vehicle; a notification unit notifying an information processor of a filter version included in the filter information piece selected by the selection unit; and a filter processing unit judging whether or not data received from the information processor is to be transferred to the ECU installed in the vehicle in accordance with a filter condition included in the filter information piece selected by the selection unit.

In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.

An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Generally disclosed herein is an approach for enabling the connection of non-PCIe accelerators as PCIe devices using a Peripheral Component Interconnect Express (PCIe) abstraction layer (PAL). Once the operating system accesses and configures any on-SoC devices and accelerators using standard PCIe APIs, all PCIe configuration transactions may be routed to the PAL. The PAL's firmware may present the operating system with a virtual PCIe space that contains all available SoC PCIe and non-PCIe devices. The firmware of the PAL may translate PCIe configuration transactions into device-specific configuration transactions.

A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.