A method and system configured to receive a first report from a computer peripheral device by a receiver, determine that the first report is corrupted or received at a rate slower than the first report rate, compute a current trajectory of the computer peripheral device based on one or more intervals of movement data in the first report, compute a predicted trajectory of the computer peripheral device based on the first report, compute an incremental displacement of the computer peripheral device based on the predicted trajectory. The method and system can further generate data indicative of a position or displacement of the computer peripheral device based on the predicted trajectory of the computer peripheral device and send the data indicative of a position or displacement of the computer peripheral device at an interval that is less than twice a period of the first report rate to the host computing device.

According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Pairing of an external device using a random user action is disclosed herein. An example method includes restricting the external device from accessing a resource. A user input receivable from the external device is identified based on a type of the external device, the user input not included in a list of previously generated user actions. In response to receipt of the user input from the external device within a threshold time period, the external device is authorized to access the resource.

In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

An expander I/O module discovery/management system includes a secondary system chassis housing an expander I/O module coupled to a server device. The server device identifies the secondary system chassis and an expander I/O module port utilized by that server device, and then generates and transmits an expander I/O module reporting communication identifying the secondary system chassis and the expander I/O module port. A primary system chassis houses a switching I/O module coupled to the expander I/O module. The switching I/O module receives the expander I/O module reporting communication and determines that the secondary system chassis identified in the expander I/O module reporting communication is different than the primary system chassis. In response, the switching I/O module assigns a virtual slot to the expander I/O module, and assigns a virtual port associated with the virtual slot to the expander I/O module port identified in the expander I/O module reporting communication.

A computing device is provided, including a processor having a plurality of pins that are electrically coupled to a connector via respective traces. The computing device may further include a memory device storing a state table that maps the plurality of pins to a respective plurality of connection protocols. The processor may be configured to implement control logic for the plurality of pins at least in part by receiving a selection of a pin of the plurality of pins. Implementing the control logic may further include receiving an updated connection protocol for the selected pin. Implementing the control logic may further include updating the state table such that the selected pin is mapped to the updated connection protocol. Implementing the control logic may further include, via the connector, establishing a connection to an external device using the updated connection protocol implemented at the selected pin.

An expander I/O module discovery/management system includes a secondary system chassis housing an expander I/O module coupled to a server device. The server device identifies the secondary system chassis and an expander I/O module port utilized by that server device, and then generates and transmits an expander I/O module reporting communication identifying the secondary system chassis and the expander I/O module port. A primary system chassis houses a switching I/O module coupled to the expander I/O module. The switching I/O module receives the expander I/O module reporting communication and determines that the secondary system chassis identified in the expander I/O module reporting communication is different than the primary system chassis. In response, the switching I/O module assigns a virtual slot to the expander I/O module, and assigns a virtual port associated with the virtual slot to the expander I/O module port identified in the expander I/O module reporting communication.

A memory device includes an input/output circuit configured to receive a status read command from a memory controller, a toggle counter configured to count a number of toggles of a signal received from the memory controller, and a status register configured to store status information of the memory device and configured to output the status information to the input/output circuit. The memory device also includes a status output controller configured to determine whether the number of toggles counted by the toggle counter corresponds to a reference number of toggles and configured to control the status register to transmit the status information to the memory controller through the input/output circuit, in response to the status read command.

Access to peripherals can be managed in a containerized environment. A management service can be employed on a computing device to detect when a container is created. When a container is created or a peripheral is connected, the management service can determine that an application running within the container should be allowed to access a peripheral. The management service can then interface with a peripheral mapper running within the container to enable the application to access the peripheral. A peripheral access manager can also be employed to isolate the peripheral to the container.

A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.