A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

Increased fairness for small vs large NVMe IO commands for accessing a non-volatile memory namespace provided by a network attached storage appliance can be realized by placing NVMe submissions received by a NVMe SQ on a first fabric queue set or a second fabric queue set based on a fairness policy. The first fabric queue set accesses the namespace via a first fabric connection. The second fabric queue set accesses the namespace via a second fabric connection. Accessing the namespace via the fabric connections results in NVMe completions that are merged from the fabric queue sets onto an NVMe completion queue. A process producing the NVMe submissions and receiving the resulting NVMe completions may be unaware of the multiple fabric queue sets.

Examples described herein relate to executing a poller to poll for received communications over multiple transport layer protocols from a connection to identify a received communication from one of the multiple transport layer protocols and identify a second received communication from a different one of the multiple transport layer protocols. A change to the different one of the multiple transport layer protocols occurs in response to failure of the one of the multiple transport layer protocols or slow transport rate using the one of the multiple transport layer protocols. In some examples, the poller is executed in user space and transport layer protocol processing of the received communication and second received communication occur in kernel space.

In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

Embodiments are disclosed for a system for coupling with at least one vehicle cable for communication with components of an infotainment system. In one example, the system includes a housing and a domain controller with hardware components enclosed within the housing. The system may further include a first connector interface arranged at a first side of the housing, the first connector interface including all connections for the domain controller.

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

In a data access method, a network device receives access requests sent by a plurality of clients connected to the network device, and sends the access requests to an access queue of a storage unit. The storage unit executes the access requests in the access queue, and returns processing results of the access requests of the plurality of clients. The network device returns the processing results that are of the access requests and that are returned by the storage unit to the clients corresponding to the access requests.

Described are platforms, systems, and methods for processing a chain of operations through an input output (IO) subsystem without central processing unit (CPU) involvement. In one aspect, a computer-implemented method comprises: providing, via the CPU, the chain of operations to the IO subsystem, wherein the IO subsystem is coupled to the one or more processors over Peripheral Component Interconnect Express (PCIe); processing, with the IO subsystem, the chain of operations by: retrieving, from a memory, data associated with the chain of operations; executing each of the operations in the chain to determine an output based on the data and output determined for any prior executed operation in the chain; and providing the output of each the executed operations for execution of the respective next operation in the chain; and providing, via the IO subsystem, an output for the chain of operations to the CPU.

A first processing unit for a computer server apparatus includes a first circuit configured to process a first type of data to be transmitted and received over a communication channel in accordance with a peripheral component interconnect express (PCIe) protocol, a second circuit configured to process a second type of data to be transmitted and received over the communication channel in accordance with a compute express link (CXL) protocol, and an optical communication interface configured to modulate the first type of data and the second type of data into a first signal in a PAM format to be transmitted over the communication channel to a second processing unit and receive, from the second processing unit over the communication channel, a second signal including either one of the first type of data and the second type of data modulated in the PAM format.