A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels.

A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

A method for supporting TCM communication by a BIOS of an ARM server, including: setting an access mode of a LPC bus device to a 4-byte mode by means of a BIOS of an ARM server; causing the BIOS to perform data communication with a TCM chip of the LPC bus device in the 4-byte mode; in response to the BIOS reading a register by means of the LPC bus device, determining a type of the register; in response to determining that the type of the register is a specific FIFO register, changing a control register from the 4-byte mode to a single-byte mode, and performing single-byte read-write on the specific FIFO register; and in response to completion of read-write of the specific FIFO register, changing the control register to the 4-byte mode by means of the BIOS, and performing a read-write operation on other FIFO registers.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.