A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

A method, computer program product, and computing system for generating a pair of protocol endpoints within each storage system of a pair of storage systems. One protocol endpoint of the pair of protocol endpoints may be dedicated to each storage system of the pair of storage systems. One or more IO requests may be processed between one or more hosts and one or more virtual volumes within the pair of storage systems via the pair of protocol endpoints.

The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

Various aspects include a continuous authentication system for a storage system. The continuous authentication system includes a host having an encryption unit. The continuous authentication system includes a storage device having a decryption unit. The continuous authentication system includes a first physical connection between the host and the storage device. The first physical connection may be configured to transfer I/Os. The continuous authentication system may include a second physical connection between the host and the storage device. The encryption unit may be configured to encrypt a continuous authentication signal. The host may be configured to transmit the continuous authentication signal through the second physical connection. The storage device may be configured to receive the continuous authentication signal through the second physical connection. The decryption unit may be configured to decrypt the continuous authentication signal. When the second physical connection is tampered with, the storage device may stop processing the I/Os.

Methods, systems, and devices for dynamic channel mapping for a memory system are described. In one example, the memory system may include a memory device having a first set of pins that are associated with a channel, and a host device, coupled with the memory device, having a second set of pins that are associated with the channel. The host device may include a controller configured to receive signaling from the memory device for a channel mapping operation, determine a channel mapping (e.g., a mapping of pins, a mapping between pins of the channel and information positions of the channel) based at least in part on the received signaling, and communicate information with the memory device via the channel based at least in part on the determined channel mapping.

A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.

A processor includes issuing units to issue a read access request to a storage, a cache including banks capable of holding first data divided from data read from the storage, a switch interconnecting the issuing units and the banks, and a data distribution unit disposed between the issuing units and the switch. The switch outputs one of read access requests to a bank that is a read target, when each of read target data of the read access requests issued from the issuing units is one of second data included in the first data, and the first data read from the bank is output to the data distribution unit. The data distribution unit outputs each of the second data, divided from the first data received from the switch, in parallel to an issuing unit that is an originator of the read access request.