An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request.

A portable device provided includes a main processor, an IO processor, a channel port coupled between the main processor and the IO processor, and at least one I/O component coupled to the IO processor. The channel port includes a plurality of channels. The main processor and the IO processor are configured to occupy one of the channels for transmitting a first command therebetween and release the occupied channel after a process is performed according to the first command.

A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation.

A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation.

Various embodiments of systems and methods to interleave high priority key-value transactions together with lower priority transactions, in which both types of transactions are communicated over a shared input-output medium. In various embodiments, a central-processing-unit (CPU) initiates high priority key-value transactions by communicating via the shared input-output medium to a key-value-store. In various embodiments, a medium controller blocks or delays lower priority transactions such that the high priority transactions may proceed without interruption. In various embodiments, both of the types of transactions are packet-based, and the system interrupts a lower priority transaction at a particular packet, then completes the high priority transaction, then completes the lower priority transaction. In various embodiments, a network-interface-card (NIC) reduces latency of key-value transactions in a distributed data store by delaying any packet or transaction that may interrupt or prevent immediate delivery of a key to a destination server holding a key value.

Various embodiments of systems and methods to interleave high priority key-value transactions together with lower priority transactions, in which both types of transactions are communicated over a shared input-output medium. In various embodiments, a central-processing-unit (CPU) initiates high priority key-value transactions by communicating via the shared input-output medium to a key-value-store. In various embodiments, a medium controller blocks or delays lower priority transactions such that the high priority transactions may proceed without interruption. In various embodiments, both of the types of transactions are packet-based, and the system interrupts a lower priority transaction at a particular packet, then completes the high priority transaction, then completes the lower priority transaction. In various embodiments, a network-interface-card (NIC) reduces latency of key-value transactions in a distributed data store by delaying any packet or transaction that may interrupt or prevent immediate delivery of a key to a destination server holding a key value.

A system and method for enabling an application (125, 305, 310, 315) and a storage device (120) to be more aware of each other may include a computer (105), a processor (110), and a memory (115) as well as the storage device (120). An application (125, 305, 310, 315) stored in the memory may communicate with a user space device driver (130). The user space device driver (130) may include a Mode Configure Module (320) to receive an application profile (405, 430, 435) from the application (125, 305, 310, 315) and an Application Aware Module (325) to receive I/O commands (555) from the application (125, 305, 310, 315) and place them in command queues (510, 515, 520, 525, 535, 540, 545, 550) according to the application profile (405, 430, and 435). The I/O commands (555) may then be sent to the storage device (120).

A system and method for enabling an application (125, 305, 310, 315) and a storage device (120) to be more aware of each other may include a computer (105), a processor (110), and a memory (115) as well as the storage device (120). An application (125, 305, 310, 315) stored in the memory may communicate with a user space device driver (130). The user space device driver (130) may include a Mode Configure Module (320) to receive an application profile (405, 430, 435) from the application (125, 305, 310, 315) and an Application Aware Module (325) to receive I/O commands (555) from the application (125, 305, 310, 315) and place them in command queues (510, 515, 520, 525, 535, 540, 545, 550) according to the application profile (405, 430, and 435). The I/O commands (555) may then be sent to the storage device (120).

A method and an apparatus for using a serial port device in a time division multiplexing manner are provided. The apparatus includes a first serial port, a second serial port, a switching circuit, and a signal interface, where the switching circuit selects to receive data sent; the first serial port sends first data to a first serial port device; the second serial port receives second data sent by a second serial port device, and when it is determined that the second data indicates that the second serial port device needs to receive third data sent by the second serial port, instructs the switching circuit to select to receive the third data sent; and the second serial port sends the third data to the second serial port device. Therefore, the first serial port and the second serial port can use corresponding serial port devices in a time division multiplexing manner.

A method and an apparatus for using a serial port device in a time division multiplexing manner are provided. The apparatus includes a first serial port, a second serial port, a switching circuit, and a signal interface, where the switching circuit selects to receive data sent; the first serial port sends first data to a first serial port device; the second serial port receives second data sent by a second serial port device, and when it is determined that the second data indicates that the second serial port device needs to receive third data sent by the second serial port, instructs the switching circuit to select to receive the third data sent; and the second serial port sends the third data to the second serial port device. Therefore, the first serial port and the second serial port can use corresponding serial port devices in a time division multiplexing manner.