Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive RTP data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack. In this manner, the AP's scheduler can coordinate/accommodate digital audio tasks within the context of its other tasks (e.g., to enable intelligent sleep and wake-up operation, load balancing, memory usage, and/or any number of other processor management functions).

A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.

Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

An arbiter that performs accelerated arbitration by approximating relative ages including a memory, blur logic, and grant logic. Multiple entries arbitrate for one or more resources. The memory stores age values each providing a relative age between each pair of entries, and further stores blurred age values. The entries are divided into subsets in which each entry belongs to only one subset. The blur logic determines each blurred age value to indicate a relative age between an entry of a first subset and an entry of a different subset for each pair of subsets. The grant logic grants access by an entry to a resource based on relative age using corresponding age values when comparing relative age between entries within a common subset, and using corresponding blurred age values when comparing relative age between entries in different subsets. Each blurred age value represents multiple age values to simplify arbitration.

Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

A Serial Peripheral Interface (SPI) master (110) and method therein for transferring data to a peripheral device in a data communication and processing system (100) are disclosed. The SPI master (110) comprises a memory (111) comprising a list of packets, each packet comprises data associated with a time parameter indicating at which time the data is to be transferred to the peripheral device. The time parameter is configurable. The SPI master further comprises a serial transmit and receive unit (112) to transfer the data in the list at a time according to the time parameter associated with the data.

According to one embodiment, there is provided an evaluation apparatus including a first data bus and a transmission device. The transmission device is electrically connected to the first data bus at an output side thereof and configured to receive data and another signal different from the data. The transmission device is configured to supply the data to the first data bus in a first period during which a valid signal is in an active level, and supply the another signal to the first data bus in a second period during which the valid signal is in a non-active level.