Disclosed are a data transmission apparatus and method, used for transmitting data between a transmitter and a receiver connected by N data lines, N being an integer greater than 1. The method comprises: sending a plurality of data units one by one; on each transmission signal, inverting the level of one and only one data line corresponding to the currently sent data unit; extracting the transmission signal, and decoding the data unit corresponding to the data line according to the data line of which level is inverted among the N data lines; and sampling the data unit and then outputting.

An apparatus and a method for bundling two data channels via a point-to-point connection, is described herein. Sequences of data from a first data channel are transmitted via a first line and sequences of data from a second data channel are transmitted via a second line to a multiplexing apparatus. A data gap having a predefined size is arranged between two sequences of first data in each case. The data from the second data channel are transmitted to a buffer and, if the buffer has been filled with second data having a predefined size, are inserted into the data from the first data channel. A third data channel is formed at the output of the multiplexing apparatus using these first data and second data and is transmitted to a third line. The third data channel therefore has a bundling of sequences of first data and sequences of second data.

A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Embodiments of the present invention provide a method and a system for managing a storage system. In one embodiment of the present invention, there is provided a method for managing a storage system, where the storage system comprises a first controller, a second controller, a first communication area as well as a second communication area. The method comprising: with respect to a storage device in the storage system, in response to the first controller successfully accessing the storage device, writing to the first communication area a first state that indicates a state relationship between the first controller and the storage device, where the first communication area is readable and writable to the first controller and readable to the second controller; reading from the second communication area a second state that indicates a state relationship between the second controller and the storage device, where the second communication area is readable to the first controller and readable and writable to the second controller; and in response to the second state indicating that the second controller successfully accesses the storage device, initializing the storage system. In one embodiment of the present invention, there is further provided a corresponding system and apparatus.

Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the access requests, based on a result of comparing the progress levels measured by the measuring circuits of the first arithmetic processors.

A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.

Method for temporally synchronizing the output of signals and/or temporally synchronizing the processing of captured signals on a plurality of input and/or output channels of an electronic circuit, comprising the following steps: (a) combining a number of channels, in particular a proportion of all channels of the circuit, to form a logical group; (b) retrieving the channel latency of each channel belonging to the group from a data source; (c) determining the greatest channel latency from all retrieved channel latencies and at least temporarily storing the greatest channel latency as the group latency; (d) for each channel belonging to the group: determining the temporal difference between the group latency and the retrieved channel latency of the respective channel and storing the determined difference as a channel-associated latency offset in a memory, in particular a memory of the circuit; and (e) influencing the signal propagation via a respective channel on the basis of at least its respective stored latency offset.