An electronic circuit device for acquiring an analog signal. The device comprising: a data line, one or more control lines (of which at least a clock line, and configured for transmitting a stored digital measurement result using the data line and the one or more control lines, in accordance with a synchronous serial communication protocol; a detection means for recognizing a synchronization pulse on one of the one or more control lines or on the data line; wherein the device is configured for repetitively measuring the analog signal or for measuring the analog signal triggered by the synchronization pulse; and for storing one or more digital measurement results or combinations thereof when triggered by the synchronization pulse.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Disclosed are a data transmission apparatus and method, used for transmitting data between a transmitter and a receiver connected by N data lines, N being an integer greater than 1. The method comprises: sending a plurality of data units one by one; on each transmission signal, inverting the level of one and only one data line corresponding to the currently sent data unit; extracting the transmission signal, and decoding the data unit corresponding to the data line according to the data line of which level is inverted among the N data lines; and sampling the data unit and then outputting.

Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

A serial transmission system includes a first storage circuit, a second storage circuit, a control circuit, and a serial processing circuit. The first storage circuit is configured to store data-to-be-transmitted of a plurality of users. The second storage circuit is coupled to the first storage circuit. The control circuit is configured to control the second storage circuit to receive the data-to-be-transmitted from the first storage circuit. The serial processing circuit is configured to receive the data-to-be-transmitted from the second storage circuit in series, and output a plurality of multi-user packets.

A device for controlling a transfer of information from a plurality of electronic components through a communication bus to a host device, comprising a chain of processing blocks connected to the electronic components, each of the processing blocks associated with one, or a set, of the electronic components, which processing blocks are arranged such that during the transfer of information an authorization signal propagates through the chain of processing blocks and, when the authorization signal encounters a processing block associated with one of the electronic components or one of the sets of electronic components which contains an information value to be transferred, effecting the transfer of the information value through the communication bus to the host device. The processing blocks are arranged to coordinate their processing in accordance with a clock signal generated independent of a propagation status of the authorization signal within the chain of processing blocks.

Provided are a synchronization control method, a chip, an electronic device and a storage medium. A master device sets a reference time for a plurality of slave devices wirelessly connected to the master device; and determines a target count value K of a connection event and an offset time of a respective slave device for each of the plurality of slave devices. The master device transmits the target count value of the connection event and the offset time to the respective slave device, so that each of the plurality of slave devices performs control based on the target count value of the connection event and the offset time of the respective slave device, so as to perform a task at the reference time.

System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

Information processing is disclosed. For instance, a first polling interval between a current polling operation and a previous polling operation is polled, the first polling interval indicating a time period from an end of the previous polling operation to a start of the current polling operation. An execution status of the current polling operation is obtained, the execution status indicating whether an object to be polled for the current polling operation is obtained. Further, based on the first polling interval and the execution status, a second polling interval is determined between the current polling operation and the next polling operation, the second polling interval indicating a time period from an end of the current polling operation to a start of the next polling operation. In this way, the solution can provide a stable and efficient adaptive polling.