A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Calibrating devices communicating on the shared bus can assist in reducing conflicts on the bus and the resulting loss of data. For example, the timing of transmission of data from one device to another device on the shared bus may be adjusted to compensate for delays on the shared bus. For example, the transmitting device may adjust transmission to an earlier time than the programmed time by an amount proportional to a known delay, such that the signal arrives at a receiving device at the programmed time. When the adjustment is not able to obtain a desired alignment or would cause conflicts on the shared data bus, the timing may be adjusted to delay the transmission, rather than advance the transmission, such that the adjusted transmission time results in the receipt of the signal at the receiving device in an unused time window after the programmed time.

Calibrating devices communicating on the shared bus can assist in reducing conflicts on the bus and the resulting loss of data. For example, the timing of transmission of data from one device to another device on the shared bus may be adjusted to compensate for delays on the shared bus. For example, the transmitting device may adjust transmission to an earlier time than the programmed time by an amount proportional to a known delay, such that the signal arrives at a receiving device at the programmed time. When the adjustment is not able to obtain a desired alignment or would cause conflicts on the shared data bus, the timing may be adjusted to delay the transmission, rather than advance the transmission, such that the adjusted transmission time results in the receipt of the signal at the receiving device in an unused time window after the programmed time.

Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

A function processing service may receive a request to execute source code. The source code may include instructions to perform a function. The function processing service may determine whether at least one hardware acceleration condition has been satisfied for the function. If at least one hardware acceleration condition has been satisfied, the instructions in the source code may be translated into hardware-specific code corresponding to a hardware circuit. The hardware circuit may be configured based on the hardware-specific code, and the hardware circuit may perform the function. The function processing service may then provide the result obtained from the hardware circuit to the requesting entity.

A method for accessing a data bus includes setting a first-come-first-served basis for determining priorities between masters in addition to a fixed priority being set between the same masters. A number of master ports are connected to a number of masters, and a number of slave ports are connected to a number of slaves. First and second multiplexers are connected between the master ports and the slave ports, a number of decoders are connected to the second multiplexers, and a number of arbiters are connected to the first multiplexers. The master ports have a fixed priority, but each arbiter, in receiving an access-request signal sent by a master port, can determine an order as to which of multiple master ports can access a slave port according to a combination of the fixed priority basis and the first-come-first-served basis. A system and a relevant device are also disclosed.

A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.