Patent classifications
G06F13/3625
Mixed-mode radio frequency front-end interface
The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.
Method for arbitrating access to a shared memory, and corresponding electronic device
Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.
BUNDLING OF CAMERA AND RADAR RAW DATA CHANNELS
An apparatus and a method for bundling two data channels via a point-to-point connection, is described herein. Sequences of data from a first data channel are transmitted via a first line and sequences of data from a second data channel are transmitted via a second line to a multiplexing apparatus. A data gap having a predefined size is arranged between two sequences of first data in each case. The data from the second data channel are transmitted to a buffer and, if the buffer has been filled with second data having a predefined size, are inserted into the data from the first data channel. A third data channel is formed at the output of the multiplexing apparatus using these first data and second data and is transmitted to a third line. The third data channel therefore has a bundling of sequences of first data and sequences of second data.
Data transmission method between a primary master and primary slave via a bus line and between sub-slaves via the same bus line
Method for digital, bidirectional data transmission between a position measuring system (3-7) and a motor control device (1) and/or an evaluation unit based on the transmission of frames (34, 35, 36) of a predefined bit length in chronologically sequential time slots (28-30), wherein a primary master (1) communicates via a two wire bus line (2) with the position measuring system (3-7) and/or the motor unit (11, 14) and/or the evaluation unit with a primary slave (3) disposed there, and that additional sub-slaves (12, 15) can be coupled in parallel to the primary slave (3), which sub-slaves communicate on the same bus line (2), which the primary master (1) uses with the primary slave (3).
METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR INFORMATION PROCESSING
Information processing is disclosed. For instance, a first polling interval between a current polling operation and a previous polling operation is polled, the first polling interval indicating a time period from an end of the previous polling operation to a start of the current polling operation. An execution status of the current polling operation is obtained, the execution status indicating whether an object to be polled for the current polling operation is obtained. Further, based on the first polling interval and the execution status, a second polling interval is determined between the current polling operation and the next polling operation, the second polling interval indicating a time period from an end of the current polling operation to a start of the next polling operation. In this way, the solution can provide a stable and efficient adaptive polling.
Procedures for improving efficiency of an interconnect fabric on a system on chip
Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
Method for managing access to a shared bus and corresponding electronic device
In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
Configurable packet arbitration with minimum progress guarantees
Systems, apparatuses, and methods for implementing a configurable packet arbiter with minimum progress guarantees are described. An arbiter includes at least control logic, a plurality of counters, and a tunables matrix. The tunables matrix stores values for a plurality of configurable parameters for the various transaction sources of the arbiter. These parameter values determine the settings that the arbiter uses for performing arbitration. One of the parameters is a minimum progress guarantee value that specifies how many times each source should be picked per interval. The minimum progress guarantee helps to reduce arbitration-related jitter. Also, the arbiter includes a grant counter for each source. After the minimum progress guarantees are satisfied, the arbiter selects the source with the lowest grant counter among the sources with packets eligible for arbitration. Then, the arbiter increments the grant counter of the winning source by a grant increment amount specific to the source.
Protecting against memory corruption and system freeze during power state transitions in a multi-power domain system
A system may include a switchable power domain configured to selectively be powered on and powered off during operation of the system and an always-on power domain configured to remain powered on during operation of the system, the always-on power domain including a power management unit. The power management unit may be configured to, in response to a shut down condition for powering down the switchable power domain, determine a state of a bus transaction on a communication bus between the switchable power domain and the always-on power domain and control one or more control signals for controlling the communication bus in order to manipulate completion of the bus transaction to prevent at least one of corruption of data of the bus transaction and a system freeze associated with the bus transaction.
Communication interface control system
A system includes a controller for controlling communication between a first device and a second device connected by way of a communication interface. The controller that is associated with the first device is configured to receive a communication request from a processor of the first device for communicating with the second device. Based on the communication request, the controller is further configured to retrieve a set of instructions from an instruction memory that is associated with the first device. Further, the controller is configured to control the communication interface at each cycle of a clock signal by executing each instruction thus controlling the communication between the first and second devices at each cycle of the clock signal.