A method, at a terminal having at least one associated graphical user interface(s)(GUI)(s), comprising: receiving input data, at one or more I/O device(s) associated with and communicatively connected to the terminal, selecting one or more file object(s) displayed on the at least one associated graphical user interface(s); retrieving, from a database stored on a computer-readable medium, parameters associated with one or more criteria for performing a sequence of one or more commands; accessing properties of file(s) associated with the one or more file objects; comparing the properties of the file(s) with the parameters associated with one or more criteria to determine which criteria are met; retrieving, from a database stored on a computer-readable medium, sequences of one or more commands to be performed under specified conditions; and calculating and initiating the appropriate sequence of commands. A terminal, system, and computer readable medium are also disclosed.

A method, at a terminal having at least one associated graphical user interface(s)(GUI)(s), comprising: receiving input data, at one or more I/O device(s) associated with and communicatively connected to the terminal, selecting one or more file object(s) displayed on the at least one associated graphical user interface(s); retrieving, from a database stored on a computer-readable medium, parameters associated with one or more criteria for performing a sequence of one or more commands; accessing properties of file(s) associated with the one or more file objects; comparing the properties of the file(s) with the parameters associated with one or more criteria to determine which criteria are met; retrieving, from a database stored on a computer-readable medium, sequences of one or more commands to be performed under specified conditions; and calculating and initiating the appropriate sequence of commands. A terminal, system, and computer readable medium are also disclosed.

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication.

An I3C master receives a max read length and a max write length from an I3C slave. Then, when transmitting/receiving data to/from the I3C slave, the I3C master controls transmission/reception of the data so that the data to be transferred in one data transfer has a data length equal to or shorter than the max read length and the max write length, and transmits transfer length information indicating the data length of the data to be transferred, prior to data transfer of the data. The present technology is applicable to a bus IF, for example.

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Devices, systems and methods for controlling electrical loads in one or more areas. A method includes transmitting, with a microcontroller via a transceiver, a sync packet including a unique address of the lighting fixture control module to a bus. The method includes listening, via the transceiver, on the bus. The method includes placing the microcontroller into a master operation mode when a master sync timeout period expires without receiving a second sync packet including a unique address for a second master device from the bus. The method includes placing the microcontroller into a subordinate operation mode when the second sync packet is received from the bus during the master sync timeout period.