The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

The first buffers forward data from the first device to the respective corresponding second devices through the respective buses while the second buffers forward data from the respective corresponding second devices to the first device through the respective buses. In response to a simultaneous data transmission request to simultaneously transmit data from the first device to the second devices, the switch controller switches the first buffer into a data-forwarding enable state, and switches the second buffer into a data-forwarding disable state, for simultaneous data transmission from the first device to the plurality of the second devices. The pseudo-response generator generates pseudo-response signals acting as a plurality of response signals that the second devices transmit to the first device as a result of the simultaneous data transmission, and transmits the plurality of the pseudo-response signals to the first device. This configuration achieves simultaneous access to multiple devices.

The first buffers forward data from the first device to the respective corresponding second devices through the respective buses while the second buffers forward data from the respective corresponding second devices to the first device through the respective buses. In response to a simultaneous data transmission request to simultaneously transmit data from the first device to the second devices, the switch controller switches the first buffer into a data-forwarding enable state, and switches the second buffer into a data-forwarding disable state, for simultaneous data transmission from the first device to the plurality of the second devices. The pseudo-response generator generates pseudo-response signals acting as a plurality of response signals that the second devices transmit to the first device as a result of the simultaneous data transmission, and transmits the plurality of the pseudo-response signals to the first device. This configuration achieves simultaneous access to multiple devices.

A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

The present disclosure provides an access arbitration system and method for a plurality of I2C communication-based master devices. The system includes: a slave device; a plurality of master devices, respectively connected to the slave device through I2C buses; and an arbitration logic controller, respectively connected to the plurality of master devices. When the master devices need to access the slave device, the master devices send access requests for an I2C bus access permission to the arbitration logic controller, the arbitration logic controller determines, based on the access requests of the master devices, the master device that establishes a communication connection with the slave device, and sends a connection confirmation instruction to the corresponding master device, and the master device that receives the connection confirmation instruction establishes the communication connection with the slave device. In the present disclosure, the reliability of system operation is improved.

A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.

A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.

A wireless network system can be provided with a one-way communication link for communicating a beacon signal between beacon circuitries of two electronic devices. According to information stored in the beacon signal, the device that receives the beacon signal can activate a primary communication circuitry to enable communication of primary communication data signals with a primary communication circuitry of the device that transmitted the beacon signal. The beacon circuitries of the two devices may require less power than the primary communication circuitries of the two devices.

A wireless network system can be provided with a one-way communication link for communicating a beacon signal between beacon circuitries of two electronic devices. According to information stored in the beacon signal, the device that receives the beacon signal can activate a primary communication circuitry to enable communication of primary communication data signals with a primary communication circuitry of the device that transmitted the beacon signal. The beacon circuitries of the two devices may require less power than the primary communication circuitries of the two devices.