Isochronous channels may be used for transporting non-isochronous data between components in an electronic device, such as when non-isochronous data is aggregated from multiple non-isochronous data streams to achieve a high peak-to-average bandwidth. The aggregated non-isochronous data sources may include data streams from general-purpose communications interfaces for interconnecting components or sub-systems of components within an electronic device. For example, I2C networks for control and programming of components may be connected to other I2C networks through an isochronous channel, such as a differential pair of Soundwire SWI3S wires.

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current. In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is pumped from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current. In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is pumped from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.

A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

An information processing system includes an information processing device, a computational processing device group, and a relay device. The information processing device corresponds to a host in the system. The computational processing device group includes a plurality of computational processing devices and corresponds to input/output (I/O) devices. The relay device has an expansion bus to which the information processing device and the computational processing device group are capable of connecting. The information processing device transmits data via the relay device to the computational processing device group. The computational processing device group executes distributed processing between the computational processing devices based on the data and transmits an execution result via the relay device to the information processing device.

A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

A multi-endpoint adapter device includes a splitter device that is coupled to a network port and a plurality of endpoint subsystems that are each coupled to a processing subsystem. The splitter device receives, via the network port, a first data payload, and identifies both a first data sub-payload that is included in the first data payload and that is associated with a first endpoint subsystem included in the plurality of endpoint subsystems and a second data sub-payload that is included in the first data payload and that is associated with a second endpoint subsystem included in the plurality of endpoint subsystems. The splitter device then splits the first data payload into the first data sub-payload and the second data sub-payload, and forwards both the first data sub-payload to the first endpoint subsystem and the second data sub-payload to the second endpoint subsystem.

An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.