G06F13/4009

Self-tune controller

Example implementations relate to a self-tune controller. For example, the self-tune controller may poll, via an out-of-band data stream, low-level operation information about a processor or a bus of a computing system under a present workload. At least some of the low-level operation information may be descriptive of a nature of traffic on the bus. The self-tune controller may program, via an out-of-band control signal, a setting of the computing system for the present workload based on the low-level operation information.

REDUCING COUPLING AND POWER NOISE ON PAM-4 I/O INTERFACE
20200242062 · 2020-07-30 ·

Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Interface conversion device of programmable logic controller (PLC) system and PLC system thereof
10678729 · 2020-06-09 · ·

The present disclosure relates to an interface conversion device of a programmable logic controller (PLC) system and a PLC system thereof. The interface conversion device of a PLC system according to an embodiment of the present disclosure is an interface conversion device that is applied to a PLC system including a base unit that controls an operation of the PLC system, a plurality of expansion modules that operate under the control of the base unit, and an interface that is a communication line between the base unit and each of the expansion modules, and is configured to connect between a first interface for parallel communication and a second interface for serial communication.

DIRECT DRIVE LED DRIVER AND OFFLINE CHARGE PUMP AND METHOD THEREFOR
20200125512 · 2020-04-23 ·

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is pumped from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.

DIRECT DRIVE LED DRIVER AND OFFLINE CHARGE PUMP AND METHOD THEREFOR
20200125513 · 2020-04-23 ·

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is pumped from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.

SYSTEM AND METHOD FOR SUPPORTING CHASSIS LEVEL KEEP ALIVE IN NVME-OF BASED SYSTEM

A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.

METHOD AND SYSTEM FOR COMMUNICATING OVER A BUS
20200104270 · 2020-04-02 ·

A communication system comprising: a digital serial bus, and a master device and at least one slave device connected to the bus. The master and the slave(s) are adapted to communicate according to a predefined communication protocol. The master is adapted for transmitting a continuous bitstream in the form of a plurality of frames, such that each frame comprises one or more words. Each word has a constant time duration, with the first word of each frame being a unique word transmitted by the master for indicating the start of a frame. One or more bits each word is transmitted by the master as a dominant bit; a non-dominant bit, for allowing the at least one slave to overwrite. The at least one slave is adapted for overwriting in the continuous bitstream some non-dominant bits to transmit data in a quasi-synchronous manner.

Computational memory with zero disable and error detection
11881872 · 2024-01-23 · ·

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

DIRECT DRIVE LED DRIVER AND OFFLINE CHARGE PUMP AND METHOD THEREFOR
20200081855 · 2020-03-12 ·

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in, accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is pumped from the input at one voltage to the output at another voltage through the AC halfwave while, providing a constant output voltage to the load.

LOW LATENCY INTERCONNECT PROTOCOL FOR COHERENT MULTI-CHIP COMMUNICATION
20200081857 · 2020-03-12 ·

In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices from two successive cycles are grouped. The grouped slices are encoded using an encoding scheme to produce an N-bit symbol at M-bits per cycle, alternating between high and low parts of the encoding. Plural metaframes are generated from a stream of symbols and the metaframes for each of the output ports are transmitted to the second SOC.