An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

A method of transparently inserting a virtual storage layer into a Fibre channel based storage area network (SAN) while maintaining continuous I/O operations is provided. A device is inserted between a host entity and a first storage device. The device identifies a plurality of first paths between the host entity and the first storage device, and defines a plurality of second paths by defining, for each first path among the plurality of first paths, a corresponding second path between the host entity and a second storage device. The device determines, for each of the plurality of first paths, a respective first state. The device establishes, for each of the second paths among the plurality of second paths, a second state based on the first state of the corresponding first path. The device redirects, to the second storage device, communications directed from the host entity to the first storage device, via the plurality of second paths.

Disclosed is a mobile device which comprises a CPU, a USB Type-C interface and a switching circuit. The switching circuit is configured to switch a connection line of two preset pins of the USB Type-C interface to connect UART TxD and UART RxD pins of the CPU, upon detecting that a UART cable is inserted into the USB Type-C interface.

A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th processor pin sets of the CPU are switchably electrically connected to 1st to a-th first PCI-E pin sets of the first PCI-E slot or (2N−a+1)th to 2N-th second PCI-E pin sets of the second PCI-E slot via the first switch to form PCI-E lanes whose number is a. (a+1)-th to 2N-th processor pin sets of the CPU are connected to the second input terminal of the second switch, and the second output terminal of the second switch is switchably electrically connected to (a+1)-th to 2N-th first PCI-E pin sets of the first PCI-E slot or 1st to (2N−a)th second PCI-E pin sets of the second PCI-E slot to form PCI-E lanes whose number is 2N−a, wherein 1<a<2N.

In accordance with embodiments disclosed herein, there is provided systems and methods for a serial mid-speed interface. A first component includes a phase-locked loop (PLL) to receive an input clock signal and to output an output signal, an interface controller including a clock-management state machine, and a transmitter. The interface controller is to receive the input clock signal, receive the output signal from the PLL, and generate a speed-switch packet. The transmitter is to transmit a first plurality of packets to a second component at a clock rate based on the clock signal via a mid-speed interface, transmit the speed-switch packet to the second component, and transmit a second plurality of packets to the second component at a PLL rate based on the output signal, where the PLL rate is greater than the clock rate.

A BIOS control method for PCI-E lanes includes the following steps. A BIOS obtains information of whether a first expansion card and a second expansion card are respectively inserted in a first PCI-E slot and a second PCI-E slot, and if the second expansion card is inserted in the second PCI-E slot, then the BIOS instructs a CPU to reverse the order of PCI-E lanes electrically connected between the CPU and the second PCI-E slot.

An aspect of obtaining optical signal health data in a SAN includes receiving, by a computer processor, a request for data corresponding to current operational characteristics of elements of a storage area network to which a host system computer has access. A further aspect includes instantiating, by the computer processor, a virtual host bus adapter interface on the host system computer, transmitting, via the virtual host bus adapter interface, the request to the elements in the portion of the storage area network, aggregating data received from each of the elements, and displaying the aggregated data via the computer processor.

A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.