According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

A hybrid docking station determines whether native video data exists and can be passed through to a video port or whether a virtual video processor should be activated to provide virtual video data to a video port. For example, a laptop is connected to a hybrid docking station using a USB™ 3.0 connection. The hybrid docking station recognizes that the USB™ 3.0 connection includes a native video data and passes the native video data to a DisplayPort™. By avoiding activating a virtualized video processor and using native video data, the laptop avoids installing software to communicate with the virtualized video processor and communicates with one or more displays using a native video channel. By avoiding installing software, it simplifies IT's and user's usage and experience with universal docking station.

In one aspect, an electronic device includes a switching circuit connected to a resistance circuit and ground, the resistance circuit connected to a port and the port configured to be connected in series to an external resistor and a supply voltage. A voltage at the port is a first voltage that is less than the supply voltage if the switching circuit is enabled to be a closed circuit and the voltage at the port is a second voltage that is equal to the supply voltage if the switching circuit is enabled to be an open circuit.

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

A universal serial bus (USB) signal transmission device, an operation method thereof, and a USB cable are provided. The USB signal transmission device includes a signal processing circuit, a switch circuit, and a control circuit. A first terminal of the switch circuit is coupled to a first USB circuit. A second terminal of the switch circuit is coupled to a second USB circuit. The control circuit turns off the switch circuit during a detection period to detect both terminals of the switch circuit to obtain a detection result. The control circuit turns on the switch circuit during a transmission period, and controls a transmission direction of the signal processing circuit according to the detection result.

An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.

Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

An aspect relates to an apparatus including a first pair of switching devices configured to selectively couple an application processor to a Universal Serial Bus (USB) differential data transmission lines; a USB host port connector coupled to the USB differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively.

A computer-implemented method for generating a ternary content addressable memory (TCAM) profile includes obtaining an access control list (ACL) configuration and generating the TCAM profile by parsing the ACL configuration. Based upon the parsing, one or more configuration features are identified, each of the features based upon a context and direction of packet flow identified in the configuration. The context includes an interface type and a routing configuration type. Based upon identifying each of the one or more configuration features, a corresponding feature is generated in the TCAM profile. At least one qualifier and at least one action associated with the respective feature is identified and associated with the feature in the TCAM profile.