Switch topology-aware path selection in an information processing system is provided. For example, an apparatus comprises a host device comprising a processor coupled to a memory. The host device is configured to communicate with a storage system over a network with a plurality of switches. The host device is further configured to obtain topology information associated with the plurality of switches in the network, and select a path from the host device to the storage system through one or more of the plurality of switches based at least in part on the obtained topology information.

The present application discloses a display panel and a display device. The display panel includes: a common electrode layer including a plurality of columns of first common electrodes, wherein each column of the plurality of columns of the first common electrodes includes a plurality of touch electrodes insulated from each other; and a driving module. Each of the plurality of touch electrodes is electrically connected to the driving module through one or more touch leads. A number of the touch leads corresponding to each of or adjacent ones of the plurality of touch electrodes gradually increases along a direction away from the driving module.

Deselect times can be specified for transactions that are to utilize a communication bus shared by multiple devices. A host can communicate with a multiplexer to select a channel for communication on that bus. If this host communicates with the multiplexer over the bus as well, the host can be prevented from instructing the multiplexer to deselect a channel if the bus is hung. To provide for recovery in such situations, one or more deselect times can be specified for one or more channels of a bus. If a transaction for a device on one of these channels is ongoing when the deselect time is reached, the multiplexer can automatically deselect that channel in order to enable other devices to communicate over other channels on that bus. In some embodiments, a riskiness of a transaction or device can be determined for purposes of applying or determining a relevant deselect time.

An integrated circuit for allowing a band of an external memory to be effectively used in processing a layer algorithm is disclosed. One aspect of the present disclosure relates to an integrated circuit including a first arithmetic part including a first arithmetic unit and a first memory, wherein the first arithmetic unit performs an operation and the first memory stores data for use in the first arithmetic unit and a first data transfer control unit that controls transfer of data between the first memory and a second memory of a second arithmetic part including a second arithmetic unit, wherein the second arithmetic part communicates with an external memory via the first arithmetic part.

An input switching circuit dynamically connects, based on an input mapping table, input streams to inputs of a wavefront pre-transform circuit. An output switching circuit dynamically connects, based on an output mapping table, output data at outputs of the wavefront pre-transform circuit to transport streams. A controller controls, based on a wiping command, at least one of the input and output switching circuits to alter at least one of the input and output mapping tables such that the at least one of the input and output switching circuits is disabled for connection. A first subset of the transport streams operates in a foreground mode available to a user and is transported for storage in remote storage sites at a network and a second subset of the transport streams operates in a background mode available to an administrator and is not transported for storage in the remote storage sites.

Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor.

A master-slave interchangeable power supply device, a power supply method, a host with the master-slave interchangeable power supply device, and a computer-readable storage medium for use in execution of the power supply method are provided. Upon receipt of a start command, a power control module and a power supply unit of the power supply device operate in a master mode and a slave mode respectively, and then the power supply device provides a working power to a master device to effect related configuration of the power supply device, so as to allow the power control module to switch to the slave mode and allow the working power to be provided to the master device. Therefore, given compliance with a specification of a communication bus, the power control module and the power supply unit, which function as peripheral devices, can perform a communicative function.

A PCIe-based communications system includes a first processor and a plurality of switches, the plurality of switches include a first switch and a second switch, a first link exists between the first processor and the first switch, a second link exists between the first switch and the second switch, and a first standby link is configured between the first processor and the second switch. If the first link and the second link are not faulty, communicating, by the first processor, with the second switch through the first link and the second link; or if the first link or the second link is faulty, activating the first standby link, and communicating, by the first processor, with the second switch through the activated first standby link. Thereby stability of the communications system can be improved.

Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.