A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.

A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).

Bandwidth consumption for IO paths between a storage system and host may be managed. It may be determined whether there is congestion on a front-end port (FEP) link. For example, the storage system may monitor for a notification from the switch in accordance with a Fibre Channel (FC) protocol. If a notification is received indicating congestion on an FEP link, the bandwidth thresholds (BWTs) for one or more IO paths between the storage system and one or more hosts that include the FEP link may be reduced. The host port BWTs may continue to be reduced until a congestion notification communication has not been received for a predetermined amount of time, in response to which the host port BWTs for one or more host port links on IO paths that include the FEP link may be increased. Similar techniques may be employed for an FEP link determined to be faulty.

A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.

A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.

A system comprising a pair of devices to enable communication between a first person and a second person; a body-suit to be worn by the first person; and a model replica of the body-suit configured to receive the tactile stimuli and/or the electrical stimuli from the second person and to convert the tactile stimuli and/or the electrical stimuli into the electrical signals which are conveyed to the body-suit over a network; wherein the body-suit is configured to replicate the tactile stimuli and/or the electrical stimuli of the model replica and convey the tactile stimuli and/or the electrical stimuli to the first person; and wherein the system allows a human to send a physical sensation of touch remotely to another human.

An Ethernet solid-state drive (eSSD) system includes a plurality of eSSDs, an Ethernet switch and a baseboard management controller. The Ethernet switch is coupled to each of the eSSDs, and the baseboard management controller is coupled to the each of the eSSDs and to the Ethernet switch. The baseboard management controller controls the Ethernet switch to provide to each eSSD a corresponding predetermined bandwidth that is based on bandwidth information for the eSSD that is stored in a policy table of the baseboard management controller. The at least one predetermined bandwidth may include a predetermined ingress bandwidth and a predetermined egress bandwidth for the corresponding eSSD. The at least one predetermined bandwidth may be based on a service level associated with the corresponding eSSD, and may be adaptively based on operating parameters of the corresponding eSSD.

A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.